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vllm - ✅(Solved) Fix [Bug]: Qwen3.5-27B fails to start with CPU KV cache offloading (`--kv_offloading_backend native`) while Qwen3-32B works fine [1 pull requests, 1 comments, 2 participants]

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vllm-project/vllm#36463•Fetched 2026-04-08 00:36:47
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Error Message

ValueError: Hybrid KV cache manager is disabled but failed to convert the KV cache specs to one unified type.

Root Cause

It appears that Qwen3.5-27B uses a hybrid attention architecture (likely mixing full attention and sliding window attention layers), and when --disable-hybrid-kv-cache-manager is set, the engine attempts to unify the KV cache specs into a single type but fails because the different attention types produce incompatible KV cache specs. This issue does not occur with Qwen3-32B, which uses a uniform attention architecture.

Fix Action

Fix / Workaround

============================== CPU Info

Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Address sizes: 52 bits physical, 57 bits virtual Byte Order: Little Endian CPU(s): 192 On-line CPU(s) list: 0-91,96-187 Off-line CPU(s) list: 92-95,188-191 Vendor ID: GenuineIntel Model name: Intel(R) Xeon(R) Platinum 8469C CPU family: 6 Model: 143 Thread(s) per core: 2 Core(s) per socket: 48 Socket(s): 2 Stepping: 8 CPU max MHz: 3800.0000 CPU min MHz: 800.0000 BogoMIPS: 5200.00 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req hfi avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm uintr md_clear serialize tsxldtrk pconfig arch_lbr amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities Virtualization: VT-x L1d cache: 4.5 MiB (96 instances) L1i cache: 3 MiB (96 instances) L2 cache: 192 MiB (96 instances) L3 cache: 195 MiB (2 instances) NUMA node(s): 2 NUMA node0 CPU(s): 0-47,96-143 NUMA node1 CPU(s): 48-95,144-191 Vulnerability Itlb multihit: Not affected Vulnerability L1tf: Not affected Vulnerability Mds: Not affected Vulnerability Meltdown: Not affected Vulnerability Mmio stale data: Not affected Vulnerability Retbleed: Not affected Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization Vulnerability Spectre v2: Mitigation; Enhanced IBRS, IBPB conditional, RSB filling, PBRSB-eIBRS SW sequence Vulnerability Srbds: Not affected Vulnerability Tsx async abort: Not affected

Qwen3.5-27B should be able to use CPU KV cache offloading (--kv_offloading_backend native) successfully, similar to Qwen3-32B. Either:

  1. The hybrid KV cache specs should be handled correctly when CPU offloading is enabled, or
  2. A clear and actionable error message should be provided explaining the incompatibility and suggesting a workaround.

PR fix notes

PR #36636: [Bugfix] Fix KV cache offloading for hybrid attention models (e.g. Qwen3.5-27B)

Description (problem / solution / changelog)

Purpose

Fix #36463: Qwen3.5-27B fails to start with CPU KV cache offloading (--kv_offloading_backend native) while Qwen3-32B works fine.

The root cause is that KV offloading auto-disables the Hybrid KV cache Manager (HMA) because OffloadingConnector doesn't implement the SupportsHMA interface. Without HMA, unify_hybrid_kv_cache_specs() tries to force all KV cache specs into one unified type, but fails because Qwen3.5-27B mixes FullAttentionSpec (standard attention) and MambaSpec (gated delta net / linear attention), which are fundamentally incompatible.

The fix makes OffloadingConnector implement SupportsHMA so HMA stays enabled for hybrid models. This is minimal and correct because:

  • OffloadingConnector already only manages group 0 (attention) blocks — it naturally ignores non-attention groups
  • request_finished_all_groups() simply delegates to existing request_finished() with group 0's block IDs
  • register_kv_caches() is fixed to filter to attention layers only, preventing KeyError on Mamba layers
  • The config now checks supports_hma() on the connector class before auto-disabling HMA, so connectors that support HMA keep it enabled while others are still auto-disabled

Test Plan

Added 3 unit tests in tests/v1/kv_connector/unit/test_offloading_connector.py:

  • test_supports_hma: verifies OffloadingConnector is a SupportsHMA subclass
  • test_request_finished_all_groups_delegates_to_group_0: verifies delegation uses group 0 block IDs
  • test_request_finished_all_groups_empty_block_ids: verifies empty block_ids guard

Test Result

All 13 tests in test_offloading_connector.py pass (10 existing + 3 new):

tests/v1/kv_connector/unit/test_offloading_connector.py::test_offloading_connector PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::test_request_preemption PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::test_concurrent_lookups_of_the_same_prefix PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::test_abort_loading_requests PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorHMA::test_supports_hma PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorHMA::test_request_finished_all_groups_delegates_to_group_0 PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorHMA::test_request_finished_all_groups_empty_block_ids PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorStats::test_build_kv_connector_stats_with_none PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorStats::test_build_kv_connector_stats_with_empty_dict PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorStats::test_build_kv_connector_stats_reconstructs_offload_stats PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorStats::test_aggregate_same_connector PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorStats::test_reduce PASSED
tests/v1/kv_connector/unit/test_offloading_connector.py::TestOffloadingConnectorStats::test_reset PASSED

All 47 tests in test_kv_cache_utils.py also pass.

Changed files

  • tests/v1/kv_connector/unit/test_offloading_connector.py (modified, +47/-0)
  • vllm/config/vllm.py (modified, +25/-11)
  • vllm/distributed/kv_transfer/kv_connector/v1/offloading_connector.py (modified, +18/-3)

Code Example

==============================
        System Info
==============================
OS                           : Ubuntu 22.04.5 LTS (x86_64)
GCC version                  : (Ubuntu 11.4.0-1ubuntu1~22.04.3) 11.4.0
Clang version                : Could not collect
CMake version                : Could not collect
Libc version                 : glibc-2.35

==============================
       PyTorch Info
==============================
PyTorch version              : 2.10.0+cu129
Is debug build               : False
CUDA used to build PyTorch   : 12.9
ROCM used to build PyTorch   : N/A

==============================
      Python Environment
==============================
Python version               : 3.12.13 (main, Mar  4 2026, 09:23:07) [GCC 11.4.0] (64-bit runtime)
Python platform              : Linux-5.10.134-16.3.al8.x86_64-x86_64-with-glibc2.35

==============================
       CUDA / GPU Info
==============================
Is CUDA available            : True
CUDA runtime version         : 12.9.86
CUDA_MODULE_LOADING set to   : 
GPU models and configuration : 
GPU 0: NVIDIA H20
GPU 1: NVIDIA H20
GPU 2: NVIDIA H20
GPU 3: NVIDIA H20
GPU 4: NVIDIA H20
GPU 5: NVIDIA H20
GPU 6: NVIDIA H20
GPU 7: NVIDIA H20

Nvidia driver version        : 580.82.07
cuDNN version                : Could not collect
HIP runtime version          : N/A
MIOpen runtime version       : N/A
Is XNNPACK available         : True

==============================
          CPU Info
==============================
Architecture:                    x86_64
CPU op-mode(s):                  32-bit, 64-bit
Address sizes:                   52 bits physical, 57 bits virtual
Byte Order:                      Little Endian
CPU(s):                          192
On-line CPU(s) list:             0-91,96-187
Off-line CPU(s) list:            92-95,188-191
Vendor ID:                       GenuineIntel
Model name:                      Intel(R) Xeon(R) Platinum 8469C
CPU family:                      6
Model:                           143
Thread(s) per core:              2
Core(s) per socket:              48
Socket(s):                       2
Stepping:                        8
CPU max MHz:                     3800.0000
CPU min MHz:                     800.0000
BogoMIPS:                        5200.00
Flags:                           fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req hfi avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm uintr md_clear serialize tsxldtrk pconfig arch_lbr amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
Virtualization:                  VT-x
L1d cache:                       4.5 MiB (96 instances)
L1i cache:                       3 MiB (96 instances)
L2 cache:                        192 MiB (96 instances)
L3 cache:                        195 MiB (2 instances)
NUMA node(s):                    2
NUMA node0 CPU(s):               0-47,96-143
NUMA node1 CPU(s):               48-95,144-191
Vulnerability Itlb multihit:     Not affected
Vulnerability L1tf:              Not affected
Vulnerability Mds:               Not affected
Vulnerability Meltdown:          Not affected
Vulnerability Mmio stale data:   Not affected
Vulnerability Retbleed:          Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp
Vulnerability Spectre v1:        Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:        Mitigation; Enhanced IBRS, IBPB conditional, RSB filling, PBRSB-eIBRS SW sequence
Vulnerability Srbds:             Not affected
Vulnerability Tsx async abort:   Not affected

==============================
Versions of relevant libraries
==============================
[pip3] flashinfer-python==0.6.4
[pip3] numpy==2.2.6
[pip3] nvidia-cublas-cu12==12.9.1.4
[pip3] nvidia-cuda-cupti-cu12==12.9.79
[pip3] nvidia-cuda-nvrtc-cu12==12.9.86
[pip3] nvidia-cuda-runtime-cu12==12.9.79
[pip3] nvidia-cudnn-cu12==9.10.2.21
[pip3] nvidia-cudnn-frontend==1.18.0
[pip3] nvidia-cufft-cu12==11.4.1.4
[pip3] nvidia-cufile-cu12==1.14.1.1
[pip3] nvidia-curand-cu12==10.3.10.19
[pip3] nvidia-cusolver-cu12==11.7.5.82
[pip3] nvidia-cusparse-cu12==12.5.10.65
[pip3] nvidia-cusparselt-cu12==0.7.1
[pip3] nvidia-cutlass-dsl==4.4.1
[pip3] nvidia-cutlass-dsl-libs-base==4.4.1
[pip3] nvidia-ml-py==13.590.48
[pip3] nvidia-nccl-cu12==2.27.5
[pip3] nvidia-nvjitlink-cu12==12.9.86
[pip3] nvidia-nvshmem-cu12==3.4.5
[pip3] nvidia-nvtx-cu12==12.9.79
[pip3] pyzmq==27.1.0
[pip3] torch==2.10.0+cu129
[pip3] torch_c_dlpack_ext==0.1.5
[pip3] torchaudio==2.10.0+cu129
[pip3] torchvision==0.25.0+cu129
[pip3] transformers==4.57.6
[pip3] triton==3.6.0
[conda] Could not collect

==============================
         vLLM Info
==============================
ROCM Version                 : Could not collect
vLLM Version                 : 0.17.0
vLLM Build Flags:
  CUDA Archs: 7.0 7.5 8.0 8.9 9.0 10.0 12.0; ROCm: Disabled
GPU Topology:
        GPU0    GPU1    GPU2    GPU3    GPU4    GPU5    GPU6    GPU7    NIC0    NIC1    NIC2    NIC3    NIC4    NIC5   NIC6     NIC7    NIC8    NIC9    NIC10   NIC11   NIC12   NIC13   NIC14   NIC15   NIC16   NIC17   NIC18   NIC19   NIC20  NIC21    NIC22   NIC23   NIC24   NIC25   NIC26   NIC27   NIC28   NIC29   NIC30   NIC31   CPU Affinity    NUMA Affinity  GPU NUMA ID
GPU0     X      NV18    NV18    NV18    NV18    NV18    NV18    NV18    NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     0-47,96-143     0              N/A
GPU1    NV18     X      NV18    NV18    NV18    NV18    NV18    NV18    PIX     PIX     PIX     PIX     PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     0-47,96-143     0              N/A
GPU2    NV18    NV18     X      NV18    NV18    NV18    NV18    NV18    NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     0-47,96-143     0              N/A
GPU3    NV18    NV18    NV18     X      NV18    NV18    NV18    NV18    NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX     PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     0-47,96-143     0              N/A
GPU4    NV18    NV18    NV18    NV18     X      NV18    NV18    NV18    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    48-91,144-187   1              N/A
GPU5    NV18    NV18    NV18    NV18    NV18     X      NV18    NV18    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    48-91,144-187   1              N/A
GPU6    NV18    NV18    NV18    NV18    NV18    NV18     X      NV18    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX     PIX     PIX     PIX     PIX     48-91,144-187   1              N/A
GPU7    NV18    NV18    NV18    NV18    NV18    NV18    NV18     X      SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    48-91,144-187   1              N/A
NIC0    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS      X      PIX     PIX     PIX     PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC1    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX      X      PIX     PIX     PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC2    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX      X      PIX     PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC3    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX      X      PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC4    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX      X      PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC5    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX      X     PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC6    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX     PIX     X       PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC7    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX     PIX    PIX       X      NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC8    NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE     X      PIX     PIX     PIX     PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC9    NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX      X      PIX     PIX     PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC10   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX      X      PIX     PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC11   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX      X      PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC12   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX      X      PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC13   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX     PIX      X      PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC14   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX     PIX     PIX      X      PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC15   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX     PIX     PIX     PIX      X      SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC16   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS      X      PIX     PIX     PIX     PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC17   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX      X      PIX     PIX     PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC18   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX      X      PIX     PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC19   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX      X      PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC20   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX      X     PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC21   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX     X       PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC22   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX    PIX       X      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC23   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX    PIX      PIX      X      NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC24   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE     X      PIX     PIX     PIX     PIX     PIX     PIX     PIX
NIC25   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX      X      PIX     PIX     PIX     PIX     PIX     PIX
NIC26   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX      X      PIX     PIX     PIX     PIX     PIX
NIC27   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX      X      PIX     PIX     PIX     PIX
NIC28   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX      X      PIX     PIX     PIX
NIC29   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX     PIX      X      PIX     PIX
NIC30   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX     PIX     PIX      X      PIX
NIC31   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX     PIX     PIX     PIX      X 

Legend:

  X    = Self
  SYS  = Connection traversing PCIe as well as the SMP interconnect between NUMA nodes (e.g., QPI/UPI)
  NODE = Connection traversing PCIe as well as the interconnect between PCIe Host Bridges within a NUMA node
  PHB  = Connection traversing PCIe as well as a PCIe Host Bridge (typically the CPU)
  PXB  = Connection traversing multiple PCIe bridges (without traversing the PCIe Host Bridge)
  PIX  = Connection traversing at most a single PCIe bridge
  NV#  = Connection traversing a bonded set of # NVLinks

NIC Legend:

  NIC0: mlx5_0
  NIC1: mlx5_1
  NIC2: mlx5_2
  NIC3: mlx5_3
  NIC4: mlx5_4
  NIC5: mlx5_5
  NIC6: mlx5_6
  NIC7: mlx5_7
  NIC8: mlx5_8
  NIC9: mlx5_9
  NIC10: mlx5_10
  NIC11: mlx5_11
  NIC12: mlx5_12
  NIC13: mlx5_13
  NIC14: mlx5_14
  NIC15: mlx5_15
  NIC16: mlx5_16
  NIC17: mlx5_17
  NIC18: mlx5_18
  NIC19: mlx5_19
  NIC20: mlx5_20
  NIC21: mlx5_21
  NIC22: mlx5_22
  NIC23: mlx5_23
  NIC24: mlx5_24
  NIC25: mlx5_25
  NIC26: mlx5_26
  NIC27: mlx5_27
  NIC28: mlx5_28
  NIC29: mlx5_29
  NIC30: mlx5_30
  NIC31: mlx5_31

==============================
     Environment Variables
==============================
NVIDIA_VISIBLE_DEVICES=0,1,2,3,4,5,6,7
NVIDIA_REQUIRE_CUDA=cuda>=12.9 brand=unknown,driver>=535,driver<536 brand=grid,driver>=535,driver<536 brand=tesla,driver>=535,driver<536 brand=nvidia,driver>=535,driver<536 brand=quadro,driver>=535,driver<536 brand=quadrortx,driver>=535,driver<536 brand=nvidiartx,driver>=535,driver<536 brand=vapps,driver>=535,driver<536 brand=vpc,driver>=535,driver<536 brand=vcs,driver>=535,driver<536 brand=vws,driver>=535,driver<536 brand=cloudgaming,driver>=535,driver<536 brand=unknown,driver>=550,driver<551 brand=grid,driver>=550,driver<551 brand=tesla,driver>=550,driver<551 brand=nvidia,driver>=550,driver<551 brand=quadro,driver>=550,driver<551 brand=quadrortx,driver>=550,driver<551 brand=nvidiartx,driver>=550,driver<551 brand=vapps,driver>=550,driver<551 brand=vpc,driver>=550,driver<551 brand=vcs,driver>=550,driver<551 brand=vws,driver>=550,driver<551 brand=cloudgaming,driver>=550,driver<551 brand=unknown,driver>=560,driver<561 brand=grid,driver>=560,driver<561 brand=tesla,driver>=560,driver<561 brand=nvidia,driver>=560,driver<561 brand=quadro,driver>=560,driver<561 brand=quadrortx,driver>=560,driver<561 brand=nvidiartx,driver>=560,driver<561 brand=vapps,driver>=560,driver<561 brand=vpc,driver>=560,driver<561 brand=vcs,driver>=560,driver<561 brand=vws,driver>=560,driver<561 brand=cloudgaming,driver>=560,driver<561 brand=unknown,driver>=565,driver<566 brand=grid,driver>=565,driver<566 brand=tesla,driver>=565,driver<566 brand=nvidia,driver>=565,driver<566 brand=quadro,driver>=565,driver<566 brand=quadrortx,driver>=565,driver<566 brand=nvidiartx,driver>=565,driver<566 brand=vapps,driver>=565,driver<566 brand=vpc,driver>=565,driver<566 brand=vcs,driver>=565,driver<566 brand=vws,driver>=565,driver<566 brand=cloudgaming,driver>=565,driver<566 brand=unknown,driver>=570,driver<571 brand=grid,driver>=570,driver<571 brand=tesla,driver>=570,driver<571 brand=nvidia,driver>=570,driver<571 brand=quadro,driver>=570,driver<571 brand=quadrortx,driver>=570,driver<571 brand=nvidiartx,driver>=570,driver<571 brand=vapps,driver>=570,driver<571 brand=vpc,driver>=570,driver<571 brand=vcs,driver>=570,driver<571 brand=vws,driver>=570,driver<571 brand=cloudgaming,driver>=570,driver<571
TORCH_CUDA_ARCH_LIST=7.0 7.5 8.0 8.9 9.0 10.0 12.0
NVIDIA_DRIVER_CAPABILITIES=all
NCCL_DEBUG=INFO
VLLM_USAGE_SOURCE=production-docker-image
NCCL_IB_GID_INDEX=3
CUDA_VERSION=12.9.1
VLLM_ENABLE_CUDA_COMPATIBILITY=0
LD_LIBRARY_PATH=/usr/local/nvidia/lib64:/usr/local/cuda/lib64:/usr/local/cuda/lib64
OMP_NUM_THREADS=8
NVIDIA_VOL_MNT_PATH=/usr/local/nvidia/
PYTORCH_NVML_BASED_CUDA_CHECK=1
TORCHINDUCTOR_COMPILE_THREADS=1
TORCHINDUCTOR_CACHE_DIR=/tmp/torchinductor_root

---

ValueError: Hybrid KV cache manager is disabled but failed to convert the KV cache specs to one unified type.

---

/usr/bin/python /usr/local/bin/vllm serve Qwen/Qwen3-32B \
    --gpu-memory-utilization 0.8 \
    --served-model-name Qwen/Qwen3-32B \
    --host 0.0.0.0 \
    --tensor-parallel-size 8 \
    --port 8000 \
    --enable-prefix-caching \
    --language-model-only \
    --reasoning-parser qwen3 \
    --max-model-len 131072 \
    --disable-hybrid-kv-cache-manager \
    --kv_offloading_backend native \
    --kv_offloading_size 500

---

/usr/bin/python /usr/local/bin/vllm serve Qwen/Qwen3.5-27B \
    --enable-auto-tool-choice \
    --tool-call-parser qwen3_coder \
    --gpu-memory-utilization 0.8 \
    --served-model-name Qwen/Qwen3.5-27B \
    --host 0.0.0.0 \
    --tensor-parallel-size 8 \
    --port 8000 \
    --max-model-len 262144 \
    --enable-prefix-caching \
    --language-model-only \
    --reasoning-parser qwen3 \
    --disable-hybrid-kv-cache-manager \
    --kv_offloading_backend native \
    --kv_offloading_size 500

---

(Worker pid=38165) (Worker_TP3 pid=38165) INFO 03-09 06:04:07 [backends.py:350] Cache the graph of compile range (52, 8192) for later use
(Worker pid=38162) (Worker_TP0 pid=38162) INFO 03-09 06:04:12 [backends.py:366] Compiling a graph for compile range (52, 8192) takes 5.06 s
(Worker pid=38162) (Worker_TP0 pid=38162) INFO 03-09 06:04:13 [gpu_worker.py:424] Available KV cache memory: 68.49 GiB
(EngineCore_DP0 pid=38138) WARNING 03-09 06:04:13 [kv_cache_utils.py:1170] Hybrid KV cache manager is disabled for this hybrid model, This means we do not enable any optimizations for saving KV cache memory (e.g., dropping the KV cache outside the sliding window). The compute of layers like sliding window is still saved.
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100] EngineCore failed to start.
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100] Traceback (most recent call last):
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/engine/core.py", line 1090, in run_engine_core
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     engine_core = EngineCoreProc(*args, engine_index=dp_rank, **kwargs)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]                   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/tracing/otel.py", line 178, in sync_wrapper
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     return func(*args, **kwargs)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]            ^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/engine/core.py", line 834, in __init__
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     super().__init__(
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/engine/core.py", line 120, in __init__
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     num_gpu_blocks, num_cpu_blocks, kv_cache_config = self._initialize_kv_caches(
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]                                                       ^^^^^^^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/tracing/otel.py", line 178, in sync_wrapper
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     return func(*args, **kwargs)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]            ^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/engine/core.py", line 263, in _initialize_kv_caches
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     kv_cache_configs = get_kv_cache_configs(
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]                        ^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/core/kv_cache_utils.py", line 1553, in get_kv_cache_configs
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     global_kv_cache_groups = get_kv_cache_groups(vllm_config, merged_kv_cache_specs)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]                              ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/core/kv_cache_utils.py", line 1231, in get_kv_cache_groups
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     unify_hybrid_kv_cache_specs(kv_cache_spec)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/core/kv_cache_utils.py", line 1211, in unify_hybrid_kv_cache_specs
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     raise ValueError(
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100] ValueError: Hybrid KV cache manager is disabled but failed to convert the KV cache specs to one unified type.
(Worker pid=38162) (Worker_TP0 pid=38162) WARNING 03-09 06:04:13 [multiproc_executor.py:814] WorkerProc was terminated
RAW_BUFFERClick to expand / collapse

Your current environment

<details> <summary>The output of <code>python collect_env.py</code></summary> 
==============================
        System Info
==============================
OS                           : Ubuntu 22.04.5 LTS (x86_64)
GCC version                  : (Ubuntu 11.4.0-1ubuntu1~22.04.3) 11.4.0
Clang version                : Could not collect
CMake version                : Could not collect
Libc version                 : glibc-2.35

==============================
       PyTorch Info
==============================
PyTorch version              : 2.10.0+cu129
Is debug build               : False
CUDA used to build PyTorch   : 12.9
ROCM used to build PyTorch   : N/A

==============================
      Python Environment
==============================
Python version               : 3.12.13 (main, Mar  4 2026, 09:23:07) [GCC 11.4.0] (64-bit runtime)
Python platform              : Linux-5.10.134-16.3.al8.x86_64-x86_64-with-glibc2.35

==============================
       CUDA / GPU Info
==============================
Is CUDA available            : True
CUDA runtime version         : 12.9.86
CUDA_MODULE_LOADING set to   : 
GPU models and configuration : 
GPU 0: NVIDIA H20
GPU 1: NVIDIA H20
GPU 2: NVIDIA H20
GPU 3: NVIDIA H20
GPU 4: NVIDIA H20
GPU 5: NVIDIA H20
GPU 6: NVIDIA H20
GPU 7: NVIDIA H20

Nvidia driver version        : 580.82.07
cuDNN version                : Could not collect
HIP runtime version          : N/A
MIOpen runtime version       : N/A
Is XNNPACK available         : True

==============================
          CPU Info
==============================
Architecture:                    x86_64
CPU op-mode(s):                  32-bit, 64-bit
Address sizes:                   52 bits physical, 57 bits virtual
Byte Order:                      Little Endian
CPU(s):                          192
On-line CPU(s) list:             0-91,96-187
Off-line CPU(s) list:            92-95,188-191
Vendor ID:                       GenuineIntel
Model name:                      Intel(R) Xeon(R) Platinum 8469C
CPU family:                      6
Model:                           143
Thread(s) per core:              2
Core(s) per socket:              48
Socket(s):                       2
Stepping:                        8
CPU max MHz:                     3800.0000
CPU min MHz:                     800.0000
BogoMIPS:                        5200.00
Flags:                           fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req hfi avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm uintr md_clear serialize tsxldtrk pconfig arch_lbr amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
Virtualization:                  VT-x
L1d cache:                       4.5 MiB (96 instances)
L1i cache:                       3 MiB (96 instances)
L2 cache:                        192 MiB (96 instances)
L3 cache:                        195 MiB (2 instances)
NUMA node(s):                    2
NUMA node0 CPU(s):               0-47,96-143
NUMA node1 CPU(s):               48-95,144-191
Vulnerability Itlb multihit:     Not affected
Vulnerability L1tf:              Not affected
Vulnerability Mds:               Not affected
Vulnerability Meltdown:          Not affected
Vulnerability Mmio stale data:   Not affected
Vulnerability Retbleed:          Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp
Vulnerability Spectre v1:        Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:        Mitigation; Enhanced IBRS, IBPB conditional, RSB filling, PBRSB-eIBRS SW sequence
Vulnerability Srbds:             Not affected
Vulnerability Tsx async abort:   Not affected

==============================
Versions of relevant libraries
==============================
[pip3] flashinfer-python==0.6.4
[pip3] numpy==2.2.6
[pip3] nvidia-cublas-cu12==12.9.1.4
[pip3] nvidia-cuda-cupti-cu12==12.9.79
[pip3] nvidia-cuda-nvrtc-cu12==12.9.86
[pip3] nvidia-cuda-runtime-cu12==12.9.79
[pip3] nvidia-cudnn-cu12==9.10.2.21
[pip3] nvidia-cudnn-frontend==1.18.0
[pip3] nvidia-cufft-cu12==11.4.1.4
[pip3] nvidia-cufile-cu12==1.14.1.1
[pip3] nvidia-curand-cu12==10.3.10.19
[pip3] nvidia-cusolver-cu12==11.7.5.82
[pip3] nvidia-cusparse-cu12==12.5.10.65
[pip3] nvidia-cusparselt-cu12==0.7.1
[pip3] nvidia-cutlass-dsl==4.4.1
[pip3] nvidia-cutlass-dsl-libs-base==4.4.1
[pip3] nvidia-ml-py==13.590.48
[pip3] nvidia-nccl-cu12==2.27.5
[pip3] nvidia-nvjitlink-cu12==12.9.86
[pip3] nvidia-nvshmem-cu12==3.4.5
[pip3] nvidia-nvtx-cu12==12.9.79
[pip3] pyzmq==27.1.0
[pip3] torch==2.10.0+cu129
[pip3] torch_c_dlpack_ext==0.1.5
[pip3] torchaudio==2.10.0+cu129
[pip3] torchvision==0.25.0+cu129
[pip3] transformers==4.57.6
[pip3] triton==3.6.0
[conda] Could not collect

==============================
         vLLM Info
==============================
ROCM Version                 : Could not collect
vLLM Version                 : 0.17.0
vLLM Build Flags:
  CUDA Archs: 7.0 7.5 8.0 8.9 9.0 10.0 12.0; ROCm: Disabled
GPU Topology:
        GPU0    GPU1    GPU2    GPU3    GPU4    GPU5    GPU6    GPU7    NIC0    NIC1    NIC2    NIC3    NIC4    NIC5   NIC6     NIC7    NIC8    NIC9    NIC10   NIC11   NIC12   NIC13   NIC14   NIC15   NIC16   NIC17   NIC18   NIC19   NIC20  NIC21    NIC22   NIC23   NIC24   NIC25   NIC26   NIC27   NIC28   NIC29   NIC30   NIC31   CPU Affinity    NUMA Affinity  GPU NUMA ID
GPU0     X      NV18    NV18    NV18    NV18    NV18    NV18    NV18    NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     0-47,96-143     0              N/A
GPU1    NV18     X      NV18    NV18    NV18    NV18    NV18    NV18    PIX     PIX     PIX     PIX     PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     0-47,96-143     0              N/A
GPU2    NV18    NV18     X      NV18    NV18    NV18    NV18    NV18    NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     0-47,96-143     0              N/A
GPU3    NV18    NV18    NV18     X      NV18    NV18    NV18    NV18    NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX     PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     0-47,96-143     0              N/A
GPU4    NV18    NV18    NV18    NV18     X      NV18    NV18    NV18    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    48-91,144-187   1              N/A
GPU5    NV18    NV18    NV18    NV18    NV18     X      NV18    NV18    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    48-91,144-187   1              N/A
GPU6    NV18    NV18    NV18    NV18    NV18    NV18     X      NV18    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX     PIX     PIX     PIX     PIX     48-91,144-187   1              N/A
GPU7    NV18    NV18    NV18    NV18    NV18    NV18    NV18     X      SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    48-91,144-187   1              N/A
NIC0    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS      X      PIX     PIX     PIX     PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC1    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX      X      PIX     PIX     PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC2    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX      X      PIX     PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC3    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX      X      PIX     PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC4    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX      X      PIX    PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC5    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX      X     PIX      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC6    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX     PIX     X       PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC7    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX     PIX    PIX       X      NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC8    NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE     X      PIX     PIX     PIX     PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC9    NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX      X      PIX     PIX     PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC10   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX      X      PIX     PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC11   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX      X      PIX     PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC12   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX      X      PIX     PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC13   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX     PIX      X      PIX     PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC14   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX     PIX     PIX      X      PIX     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC15   NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE    NODE   NODE     NODE    PIX     PIX     PIX     PIX     PIX     PIX     PIX      X      SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS
NIC16   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS      X      PIX     PIX     PIX     PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC17   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX      X      PIX     PIX     PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC18   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX      X      PIX     PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC19   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX      X      PIX    PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC20   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX      X     PIX      PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC21   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX     X       PIX     PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC22   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX    PIX       X      PIX     NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC23   SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     PIX     PIX     PIX     PIX     PIX    PIX      PIX      X      NODE    NODE    NODE    NODE    NODE    NODE    NODE    NODE
NIC24   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE     X      PIX     PIX     PIX     PIX     PIX     PIX     PIX
NIC25   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX      X      PIX     PIX     PIX     PIX     PIX     PIX
NIC26   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX      X      PIX     PIX     PIX     PIX     PIX
NIC27   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX      X      PIX     PIX     PIX     PIX
NIC28   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX      X      PIX     PIX     PIX
NIC29   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX     PIX      X      PIX     PIX
NIC30   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX     PIX     PIX      X      PIX
NIC31   SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     SYS    SYS      SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE    NODE   NODE     NODE    NODE    PIX     PIX     PIX     PIX     PIX     PIX     PIX      X 

Legend:

  X    = Self
  SYS  = Connection traversing PCIe as well as the SMP interconnect between NUMA nodes (e.g., QPI/UPI)
  NODE = Connection traversing PCIe as well as the interconnect between PCIe Host Bridges within a NUMA node
  PHB  = Connection traversing PCIe as well as a PCIe Host Bridge (typically the CPU)
  PXB  = Connection traversing multiple PCIe bridges (without traversing the PCIe Host Bridge)
  PIX  = Connection traversing at most a single PCIe bridge
  NV#  = Connection traversing a bonded set of # NVLinks

NIC Legend:

  NIC0: mlx5_0
  NIC1: mlx5_1
  NIC2: mlx5_2
  NIC3: mlx5_3
  NIC4: mlx5_4
  NIC5: mlx5_5
  NIC6: mlx5_6
  NIC7: mlx5_7
  NIC8: mlx5_8
  NIC9: mlx5_9
  NIC10: mlx5_10
  NIC11: mlx5_11
  NIC12: mlx5_12
  NIC13: mlx5_13
  NIC14: mlx5_14
  NIC15: mlx5_15
  NIC16: mlx5_16
  NIC17: mlx5_17
  NIC18: mlx5_18
  NIC19: mlx5_19
  NIC20: mlx5_20
  NIC21: mlx5_21
  NIC22: mlx5_22
  NIC23: mlx5_23
  NIC24: mlx5_24
  NIC25: mlx5_25
  NIC26: mlx5_26
  NIC27: mlx5_27
  NIC28: mlx5_28
  NIC29: mlx5_29
  NIC30: mlx5_30
  NIC31: mlx5_31

==============================
     Environment Variables
==============================
NVIDIA_VISIBLE_DEVICES=0,1,2,3,4,5,6,7
NVIDIA_REQUIRE_CUDA=cuda>=12.9 brand=unknown,driver>=535,driver<536 brand=grid,driver>=535,driver<536 brand=tesla,driver>=535,driver<536 brand=nvidia,driver>=535,driver<536 brand=quadro,driver>=535,driver<536 brand=quadrortx,driver>=535,driver<536 brand=nvidiartx,driver>=535,driver<536 brand=vapps,driver>=535,driver<536 brand=vpc,driver>=535,driver<536 brand=vcs,driver>=535,driver<536 brand=vws,driver>=535,driver<536 brand=cloudgaming,driver>=535,driver<536 brand=unknown,driver>=550,driver<551 brand=grid,driver>=550,driver<551 brand=tesla,driver>=550,driver<551 brand=nvidia,driver>=550,driver<551 brand=quadro,driver>=550,driver<551 brand=quadrortx,driver>=550,driver<551 brand=nvidiartx,driver>=550,driver<551 brand=vapps,driver>=550,driver<551 brand=vpc,driver>=550,driver<551 brand=vcs,driver>=550,driver<551 brand=vws,driver>=550,driver<551 brand=cloudgaming,driver>=550,driver<551 brand=unknown,driver>=560,driver<561 brand=grid,driver>=560,driver<561 brand=tesla,driver>=560,driver<561 brand=nvidia,driver>=560,driver<561 brand=quadro,driver>=560,driver<561 brand=quadrortx,driver>=560,driver<561 brand=nvidiartx,driver>=560,driver<561 brand=vapps,driver>=560,driver<561 brand=vpc,driver>=560,driver<561 brand=vcs,driver>=560,driver<561 brand=vws,driver>=560,driver<561 brand=cloudgaming,driver>=560,driver<561 brand=unknown,driver>=565,driver<566 brand=grid,driver>=565,driver<566 brand=tesla,driver>=565,driver<566 brand=nvidia,driver>=565,driver<566 brand=quadro,driver>=565,driver<566 brand=quadrortx,driver>=565,driver<566 brand=nvidiartx,driver>=565,driver<566 brand=vapps,driver>=565,driver<566 brand=vpc,driver>=565,driver<566 brand=vcs,driver>=565,driver<566 brand=vws,driver>=565,driver<566 brand=cloudgaming,driver>=565,driver<566 brand=unknown,driver>=570,driver<571 brand=grid,driver>=570,driver<571 brand=tesla,driver>=570,driver<571 brand=nvidia,driver>=570,driver<571 brand=quadro,driver>=570,driver<571 brand=quadrortx,driver>=570,driver<571 brand=nvidiartx,driver>=570,driver<571 brand=vapps,driver>=570,driver<571 brand=vpc,driver>=570,driver<571 brand=vcs,driver>=570,driver<571 brand=vws,driver>=570,driver<571 brand=cloudgaming,driver>=570,driver<571
TORCH_CUDA_ARCH_LIST=7.0 7.5 8.0 8.9 9.0 10.0 12.0
NVIDIA_DRIVER_CAPABILITIES=all
NCCL_DEBUG=INFO
VLLM_USAGE_SOURCE=production-docker-image
NCCL_IB_GID_INDEX=3
CUDA_VERSION=12.9.1
VLLM_ENABLE_CUDA_COMPATIBILITY=0
LD_LIBRARY_PATH=/usr/local/nvidia/lib64:/usr/local/cuda/lib64:/usr/local/cuda/lib64
OMP_NUM_THREADS=8
NVIDIA_VOL_MNT_PATH=/usr/local/nvidia/
PYTORCH_NVML_BASED_CUDA_CHECK=1
TORCHINDUCTOR_COMPILE_THREADS=1
TORCHINDUCTOR_CACHE_DIR=/tmp/torchinductor_root
</details>

🐛 Describe the bug

Bug Description

Qwen3.5-27B fails to start when CPU KV cache offloading is enabled via --kv_offloading_backend native --kv_offloading_size 500, while Qwen3-32B starts successfully with the exact same offloading configuration in the same environment.

The error occurs during KV cache initialization with:

ValueError: Hybrid KV cache manager is disabled but failed to convert the KV cache specs to one unified type.

It appears that Qwen3.5-27B uses a hybrid attention architecture (likely mixing full attention and sliding window attention layers), and when --disable-hybrid-kv-cache-manager is set, the engine attempts to unify the KV cache specs into a single type but fails because the different attention types produce incompatible KV cache specs. This issue does not occur with Qwen3-32B, which uses a uniform attention architecture.

The root cause seems to be in vllm/v1/core/kv_cache_utils.py at unify_hybrid_kv_cache_specs(), which cannot reconcile the different KV cache spec types when the hybrid KV cache manager is disabled and CPU offloading is enabled simultaneously.

Expected Behavior

Qwen3.5-27B should be able to use CPU KV cache offloading (--kv_offloading_backend native) successfully, similar to Qwen3-32B. Either:

  1. The hybrid KV cache specs should be handled correctly when CPU offloading is enabled, or
  2. A clear and actionable error message should be provided explaining the incompatibility and suggesting a workaround.

Environment

  • Docker image: vllm/vllm-openai:0.17.0
  • GPU: 8× NVIDIA H20 (single node)
  • Model: Qwen/Qwen3.5-27B

How to Reproduce

✅ Qwen3-32B — Works Successfully

/usr/bin/python /usr/local/bin/vllm serve Qwen/Qwen3-32B \
    --gpu-memory-utilization 0.8 \
    --served-model-name Qwen/Qwen3-32B \
    --host 0.0.0.0 \
    --tensor-parallel-size 8 \
    --port 8000 \
    --enable-prefix-caching \
    --language-model-only \
    --reasoning-parser qwen3 \
    --max-model-len 131072 \
    --disable-hybrid-kv-cache-manager \
    --kv_offloading_backend native \
    --kv_offloading_size 500

This starts successfully and provides ~30% prefill speedup.

❌ Qwen3.5-27B — Fails to Start

/usr/bin/python /usr/local/bin/vllm serve Qwen/Qwen3.5-27B \
    --enable-auto-tool-choice \
    --tool-call-parser qwen3_coder \
    --gpu-memory-utilization 0.8 \
    --served-model-name Qwen/Qwen3.5-27B \
    --host 0.0.0.0 \
    --tensor-parallel-size 8 \
    --port 8000 \
    --max-model-len 262144 \
    --enable-prefix-caching \
    --language-model-only \
    --reasoning-parser qwen3 \
    --disable-hybrid-kv-cache-manager \
    --kv_offloading_backend native \
    --kv_offloading_size 500

Full Error Traceback

(Worker pid=38165) (Worker_TP3 pid=38165) INFO 03-09 06:04:07 [backends.py:350] Cache the graph of compile range (52, 8192) for later use
(Worker pid=38162) (Worker_TP0 pid=38162) INFO 03-09 06:04:12 [backends.py:366] Compiling a graph for compile range (52, 8192) takes 5.06 s
(Worker pid=38162) (Worker_TP0 pid=38162) INFO 03-09 06:04:13 [gpu_worker.py:424] Available KV cache memory: 68.49 GiB
(EngineCore_DP0 pid=38138) WARNING 03-09 06:04:13 [kv_cache_utils.py:1170] Hybrid KV cache manager is disabled for this hybrid model, This means we do not enable any optimizations for saving KV cache memory (e.g., dropping the KV cache outside the sliding window). The compute of layers like sliding window is still saved.
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100] EngineCore failed to start.
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100] Traceback (most recent call last):
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/engine/core.py", line 1090, in run_engine_core
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     engine_core = EngineCoreProc(*args, engine_index=dp_rank, **kwargs)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]                   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/tracing/otel.py", line 178, in sync_wrapper
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     return func(*args, **kwargs)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]            ^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/engine/core.py", line 834, in __init__
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     super().__init__(
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/engine/core.py", line 120, in __init__
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     num_gpu_blocks, num_cpu_blocks, kv_cache_config = self._initialize_kv_caches(
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]                                                       ^^^^^^^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/tracing/otel.py", line 178, in sync_wrapper
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     return func(*args, **kwargs)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]            ^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/engine/core.py", line 263, in _initialize_kv_caches
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     kv_cache_configs = get_kv_cache_configs(
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]                        ^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/core/kv_cache_utils.py", line 1553, in get_kv_cache_configs
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     global_kv_cache_groups = get_kv_cache_groups(vllm_config, merged_kv_cache_specs)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]                              ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/core/kv_cache_utils.py", line 1231, in get_kv_cache_groups
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     unify_hybrid_kv_cache_specs(kv_cache_spec)
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]   File "/usr/local/lib/python3.12/dist-packages/vllm/v1/core/kv_cache_utils.py", line 1211, in unify_hybrid_kv_cache_specs
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100]     raise ValueError(
(EngineCore_DP0 pid=38138) ERROR 03-09 06:04:13 [core.py:1100] ValueError: Hybrid KV cache manager is disabled but failed to convert the KV cache specs to one unified type.
(Worker pid=38162) (Worker_TP0 pid=38162) WARNING 03-09 06:04:13 [multiproc_executor.py:814] WorkerProc was terminated

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extent analysis

Fix Plan

To resolve the issue with Qwen3.5-27B failing to start when CPU KV cache offloading is enabled, we need to modify the unify_hybrid_kv_cache_specs function in vllm/v1/core/kv_cache_utils.py to correctly handle hybrid KV cache specs when the hybrid KV cache manager is disabled and CPU offloading is enabled.

Here are the steps to fix the issue:

  1. Modify the unify_hybrid_kv_cache_specs function: Update the function to check if CPU offloading is enabled and handle the hybrid KV cache specs accordingly.
  2. Add a check for CPU offloading: Before attempting to unify the KV cache specs, check if CPU offloading is enabled. If it is, use a different approach to handle the hybrid KV cache specs.
  3. Use a compatible KV cache spec type: When CPU offloading is enabled, use a compatible KV cache spec type that can be unified with the other specs.

Example code snippet:

def unify_hybrid_kv_cache_specs(kv_cache_spec):
    # Check if CPU offloading is enabled
    if vllm_config.kv_offloading_backend == 'native':
        # Use a compatible KV cache spec type
        unified_spec = {}
        for spec in kv_cache_spec:
            if spec['type'] == 'full_attention':
                unified_spec['type'] = 'full_attention'
                unified_spec['size'] = spec['size']
            elif spec['type'] == 'sliding_window':
                unified_spec['type'] = 'sliding_window'
                unified_spec['size'] = spec['size']
        return unified_spec
    else:
        # Handle the case where CPU offloading is not enabled
        # ...

Verification

To verify that the fix worked, run the following command:

/usr/bin/python /usr/local/bin/vllm serve Qwen/Qwen3.5-27B \
    --enable-auto-tool-choice \
    --tool-call-parser qwen3_coder \
    --gpu-memory-utilization 0.8 \
    --served-model-name Qwen/Qwen3.5-27B \
    --host 0.0.0.0 \
    --tensor-parallel-size 8 \
    --port 8000 \
    --max-model-len 262144 \
    --enable-prefix-caching \
    --language-model-only \
    --reasoning-parser qwen3 \
    --disable-hybrid-kv-cache-manager \
    --kv_offloading_backend native \
    --kv_offloading_size 500

If the model starts successfully, it indicates that the fix worked.

Extra Tips

  • Make sure to update the vllm_config object with the correct values for CPU offloading.
  • If you encounter any issues during the verification process, check the logs for any error messages and adjust the fix accordingly.

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