pytorch - ✅(Solved) Fix Conv3D does not preserve dim_order for some inputs [1 pull requests, 1 participants]

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pytorch/pytorch#177277Fetched 2026-04-08 00:42:18
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Fix Action

Fix / Workaround

CPU: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Address sizes: 46 bits physical, 48 bits virtual Byte Order: Little Endian CPU(s): 12 On-line CPU(s) list: 0-11 Vendor ID: GenuineIntel Model name: 13th Gen Intel(R) Core(TM) i7-1365U CPU family: 6 Model: 186 Thread(s) per core: 2 Core(s) per socket: 10 Socket(s): 1 Stepping: 3 CPU(s) scaling MHz: 20% CPU max MHz: 5200.0000 CPU min MHz: 400.0000 BogoMIPS: 5376.00 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb ssbd ibrs ibpb stibp ibrs_enhanced fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid rdseed adx smap clflushopt clwb intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves split_lock_detect user_shstk avx_vnni dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req hfi umip pku ospke waitpkg gfni vaes vpclmulqdq tme rdpid movdiri movdir64b fsrm md_clear serialize pconfig arch_lbr ibt flush_l1d arch_capabilities ibpb_exit_to_user L1d cache: 352 KiB (10 instances) L1i cache: 576 KiB (10 instances) L2 cache: 6.5 MiB (4 instances) L3 cache: 12 MiB (1 instance) NUMA node(s): 1 NUMA node0 CPU(s): 0-11 Vulnerability Gather data sampling: Not affected Vulnerability Indirect target selection: Not affected Vulnerability Itlb multihit: Not affected Vulnerability L1tf: Not affected Vulnerability Mds: Not affected Vulnerability Meltdown: Not affected Vulnerability Mmio stale data: Not affected Vulnerability Reg file data sampling: Mitigation; Clear Register File Vulnerability Retbleed: Not affected Vulnerability Spec rstack overflow: Not affected Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization Vulnerability Spectre v2: Mitigation; Enhanced / Automatic IBRS; IBPB conditional; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S Vulnerability Srbds: Not affected Vulnerability Tsa: Not affected Vulnerability Tsx async abort: Not affected Vulnerability Vmscape: Mitigation; IBPB before exit to userspace

PR fix notes

PR #177382: fix: propagate channels_last/channels_last_3d memory format in meta_conv

Description (problem / solution / changelog)

fix(meta): propagate channels_last/channels_last_3d memory format in meta_conv

conv3d did not preserve channels_last_3d memory format under FakeTensorMode because meta_conv always created the output via new_empty(shape_out), which defaults to contiguous format.

Mirror the logic already present in meta_convolution_backward: detect the memory format from input_tensor and weight via suggest_memory_format, then apply it to the output with .to(memory_format=...).

Fixes: https://github.com/pytorch/pytorch/issues/177277

Test plan: python test/test_fake_tensor.py FakeTensorTest.test_conv_ndhwc python test/test_fake_tensor.py FakeTensorTest.test_conv_nhwc_channels_last_weight_only python test/test_fake_tensor.py FakeTensorTest.test_conv_nhwc

cc @digantdesai @freddan80 @per @zingo @oscarandersson8218 @mansnils @Sebastian-Larsson @robell

Changed files

  • test/test_fake_tensor.py (modified, +69/-0)
  • torch/_meta_registrations.py (modified, +17/-1)

Code Example

import torch
from torch._subclasses.fake_tensor import FakeTensorMode


STRIDE = [1, 1, 1]
PAD = [0, 0, 0]
DILATION = [1, 1, 1]
GROUPS = 1

fake_mode = FakeTensorMode()
x = fake_mode.from_tensor(torch.zeros(1, 2, 6, 6, 6).to(memory_format=torch.channels_last_3d))
w = fake_mode.from_tensor(torch.zeros(4, 2, 3, 3, 3).to(memory_format=torch.channels_last_3d))
b = fake_mode.from_tensor(torch.zeros(4))

y = torch.ops.aten.conv3d.default(
        x, w, b, STRIDE, PAD, DILATION, GROUPS
    )
print(f"input size/dim_order: {x.size()}/{x.dim_order()}")
print(f"output dim_order: {y.size()}/{y.dim_order()}")

>> input size/dim_order: torch.Size([1, 2, 6, 6, 6])/(0, 2, 3, 4, 1)
>> output size/dim_order: torch.Size([1, 4, 4, 4, 4])/(0, 1, 2, 3, 4)
RAW_BUFFERClick to expand / collapse

🐛 Describe the bug

Running the torch.torch.ops.aten.conv3d.default operator does not preserve dim-order, causing an issue later in the graph as the data is wrongly interpreted.

import torch
from torch._subclasses.fake_tensor import FakeTensorMode


STRIDE = [1, 1, 1]
PAD = [0, 0, 0]
DILATION = [1, 1, 1]
GROUPS = 1

fake_mode = FakeTensorMode()
x = fake_mode.from_tensor(torch.zeros(1, 2, 6, 6, 6).to(memory_format=torch.channels_last_3d))
w = fake_mode.from_tensor(torch.zeros(4, 2, 3, 3, 3).to(memory_format=torch.channels_last_3d))
b = fake_mode.from_tensor(torch.zeros(4))

y = torch.ops.aten.conv3d.default(
        x, w, b, STRIDE, PAD, DILATION, GROUPS
    )
print(f"input size/dim_order: {x.size()}/{x.dim_order()}")
print(f"output dim_order: {y.size()}/{y.dim_order()}")

>> input size/dim_order: torch.Size([1, 2, 6, 6, 6])/(0, 2, 3, 4, 1)
>> output size/dim_order: torch.Size([1, 4, 4, 4, 4])/(0, 1, 2, 3, 4)

Versions

Collecting environment information... PyTorch version: 2.11.0.dev20251222+cpu Is debug build: False CUDA used to build PyTorch: None ROCM used to build PyTorch: N/A

OS: Ubuntu 24.04.1 LTS (x86_64) GCC version: (Ubuntu 13.3.0-6ubuntu2~24.04.1) 13.3.0 Clang version: 18.1.3 (1ubuntu1) CMake version: version 3.31.6 Libc version: glibc-2.39

Python version: 3.10.15 (main, Sep 7 2024, 18:35:38) [GCC 13.2.0] (64-bit runtime) Python platform: Linux-6.8.0-101-generic-x86_64-with-glibc2.39 Is CUDA available: False CUDA runtime version: No CUDA CUDA_MODULE_LOADING set to: N/A GPU models and configuration: No CUDA Nvidia driver version: No CUDA cuDNN version: No CUDA Is XPU available: False HIP runtime version: N/A MIOpen runtime version: N/A Is XNNPACK available: True Caching allocator config: N/A

CPU: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Address sizes: 46 bits physical, 48 bits virtual Byte Order: Little Endian CPU(s): 12 On-line CPU(s) list: 0-11 Vendor ID: GenuineIntel Model name: 13th Gen Intel(R) Core(TM) i7-1365U CPU family: 6 Model: 186 Thread(s) per core: 2 Core(s) per socket: 10 Socket(s): 1 Stepping: 3 CPU(s) scaling MHz: 20% CPU max MHz: 5200.0000 CPU min MHz: 400.0000 BogoMIPS: 5376.00 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb ssbd ibrs ibpb stibp ibrs_enhanced fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid rdseed adx smap clflushopt clwb intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves split_lock_detect user_shstk avx_vnni dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req hfi umip pku ospke waitpkg gfni vaes vpclmulqdq tme rdpid movdiri movdir64b fsrm md_clear serialize pconfig arch_lbr ibt flush_l1d arch_capabilities ibpb_exit_to_user L1d cache: 352 KiB (10 instances) L1i cache: 576 KiB (10 instances) L2 cache: 6.5 MiB (4 instances) L3 cache: 12 MiB (1 instance) NUMA node(s): 1 NUMA node0 CPU(s): 0-11 Vulnerability Gather data sampling: Not affected Vulnerability Indirect target selection: Not affected Vulnerability Itlb multihit: Not affected Vulnerability L1tf: Not affected Vulnerability Mds: Not affected Vulnerability Meltdown: Not affected Vulnerability Mmio stale data: Not affected Vulnerability Reg file data sampling: Mitigation; Clear Register File Vulnerability Retbleed: Not affected Vulnerability Spec rstack overflow: Not affected Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization Vulnerability Spectre v2: Mitigation; Enhanced / Automatic IBRS; IBPB conditional; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S Vulnerability Srbds: Not affected Vulnerability Tsa: Not affected Vulnerability Tsx async abort: Not affected Vulnerability Vmscape: Mitigation; IBPB before exit to userspace

Versions of relevant libraries: [pip3] executorch==1.2.0a0+e9d9034 [pip3] flake8==6.1.0 [pip3] flake8-breakpoint==1.1.0 [pip3] flake8-bugbear==24.4.26 [pip3] flake8-comprehensions==3.14.0 [pip3] flake8-plugin-utils==1.3.3 [pip3] flake8-pyi==23.5.0 [pip3] mypy==1.14.1 [pip3] mypy_extensions==1.1.0 [pip3] numpy==2.2.6 [pip3] nvidia-cublas-cu12==12.6.4.1 [pip3] nvidia-cuda-cupti-cu12==12.6.80 [pip3] nvidia-cuda-nvrtc-cu12==12.6.77 [pip3] nvidia-cuda-runtime-cu12==12.6.77 [pip3] nvidia-cudnn-cu12==9.5.1.17 [pip3] nvidia-cufft-cu12==11.3.0.4 [pip3] nvidia-curand-cu12==10.3.7.77 [pip3] nvidia-cusolver-cu12==11.7.1.2 [pip3] nvidia-cusparse-cu12==12.5.4.2 [pip3] nvidia-cusparselt-cu12==0.6.3 [pip3] nvidia-nccl-cu12==2.26.2 [pip3] nvidia-nvjitlink-cu12==12.6.85 [pip3] nvidia-nvtx-cu12==12.6.77 [pip3] pytorch_tokenizers==1.0.1 [pip3] torch==2.11.0.dev20251222+cpu [pip3] torchao==0.16.0+git28306f085 [pip3] torchaudio==2.10.0.dev20251222+cpu [pip3] torchdata==0.11.0 [pip3] torchsr==1.0.4 [pip3] torchtune==0.6.1 [pip3] torchvision==0.25.0.dev20251222+cpu [pip3] triton==3.3.1 [conda] Could not collect

cc @jamesr66a @chauhang @penguinwu @eellison @aorenste @bdhirsh @bobrenjc93

extent analysis

Fix Plan

To preserve the dim-order when running the torch.torch.ops.aten.conv3d.default operator, you can use the torch.nn.functional.conv3d function instead, which supports the memory_format argument. Here's an example:

import torch
import torch.nn.functional as F

# Define the input and weight tensors with the desired memory format
x = torch.zeros(1, 2, 6, 6, 6, memory_format=torch.channels_last_3d)
w = torch.zeros(4, 2, 3, 3, 3, memory_format=torch.channels_last_3d)
b = torch.zeros(4)

# Perform the convolution using torch.nn.functional.conv3d
y = F.conv3d(x, w, bias=b, stride=STRIDE, padding=PAD, dilation=DILATION, groups=GROUPS)

print(f"input size/dim_order: {x.size()}/{x.dim_order()}")
print(f"output dim_order: {y.size()}/{y.dim_order()}")

Alternatively, you can use the torch.ops.aten.conv3d.default operator with the memory_format argument set to torch.channels_last_3d for the input and weight tensors:

y = torch.ops.aten.conv3d.default(
    x.contiguous(memory_format=torch.channels_last_3d), 
    w.contiguous(memory_format=torch.channels_last_3d), 
    b, STRIDE, PAD, DILATION, GROUPS
)

Verification

To verify that the fix worked, you can check the dim-order of the output tensor y using the dim_order() method. The dim-order should match the expected value.

Extra Tips

  • Make sure to set the memory_format argument correctly for the input and weight tensors to ensure that the dim-order is preserved.
  • Use the contiguous() method to ensure that the tensors are contiguous in memory, which can improve performance.
  • Consider using the torch.nn.functional.conv3d function instead of the torch.ops.aten.conv3d.default operator for better support of the memory_format argument.

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pytorch - ✅(Solved) Fix Conv3D does not preserve dim_order for some inputs [1 pull requests, 1 participants]