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pytorch - ✅(Solved) Fix DISABLED test_correctness_add_bf16_native (__main__.TestInlineAsmElementwise) [2 pull requests, 1 comments, 2 participants]

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pytorch/pytorch#179946•Fetched 2026-04-11 06:11:29
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praguptapragupta
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praguptapraguptapytorch-bot[bot]pytorch-bot[bot]
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Root Cause

This test was disabled because it is failing on main branch (recent examples).

PR fix notes

PR #180257: [ROCm] Fix inline_asm_elementwise for ROCm

Description (problem / solution / changelog)

Fixes #179925. Fixes #179927. Fixes #180010. Fixes #179965. Fixes #179982. Fixes #179946.

The inline_asm_elementwise HOP had all assembly hardcoded as PTX and the test file was blocklisted on ROCm. This PR adds AMDGCN equivalents behind torch.version.hip guards so every test case works on both backends. The NVIDIA path is untouched throughout.

Most PTX-to-AMDGCN translations are direct (mov.f32 to v_mov_b32, f/r constraints to v). The fp16/bf16 native cases required a different approach. AMDGCN has no h constraint for 16-bit registers, so we add in f32 and convert down via v_cvt_f16_f32 and v_cvt_pk_bf16_f32.

Two Inductor codegen fixes handle AMDGCN's newline-separated instructions (PTX uses semicolons on one line). In utils.py, multiline format_node() output is split so each line gets the comment prefix. In triton.py, asm literals are double-escaped via repr() to survive two layers of Python string parsing. Both are HIP-guarded.

cc @jeffdaily @sunway513 @jithunnair-amd @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @pragupta @jerrymannil @xinyazhang @voznesenskym @penguinwu @EikanWang @jgong5 @Guobing-Chen @XiaobingSuper @zhuhaozhe @blzheng @wenzhe-nrv @jiayisunx @ipiszy @kadeng @muchulee8 @amjames @chauhang @aakhundov @coconutruben

Changed files

  • test/higher_order_ops/test_inline_asm_elementwise.py (modified, +214/-66)
  • test/run_test.py (modified, +0/-1)
  • torch/_inductor/codegen/triton.py (modified, +16/-1)
  • torch/_inductor/utils.py (modified, +11/-3)
  • torch/testing/_internal/hop_db.py (modified, +8/-0)

PR #180600: [ROCm] Fix inline_asm_elementwise for ROCm

Description (problem / solution / changelog)

Fixes #179925. Fixes #179927. Fixes #180010. Fixes #179965. Fixes #179982. Fixes #179946.

The inline_asm_elementwise HOP had all assembly hardcoded as PTX and the test file was blocklisted on ROCm. This PR adds AMDGCN equivalents behind torch.version.hip guards so every test case works on both backends. The NVIDIA path is untouched throughout.

Most PTX-to-AMDGCN translations are direct (mov.f32 to v_mov_b32, f/r constraints to v). The fp16/bf16 native cases required a different approach. AMDGCN has no h constraint for 16-bit registers, so we add in f32 and convert down via v_cvt_f16_f32 and v_cvt_pk_bf16_f32.

Two Inductor codegen fixes handle AMDGCN's newline-separated instructions (PTX uses semicolons on one line). In utils.py, multiline format_node() output is split so each line gets the comment prefix. In triton.py, asm literals are double-escaped via repr() to survive two layers of Python string parsing. Both are HIP-guarded.

cc @jeffdaily @sunway513 @jithunnair-amd @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @pragupta @jerrymannil @xinyazhang @voznesenskym @penguinwu @EikanWang @jgong5 @Guobing-Chen @XiaobingSuper @zhuhaozhe @blzheng @wenzhe-nrv @jiayisunx @ipiszy @kadeng @muchulee8 @amjames @chauhang @aakhundov @coconutruben

Changed files

  • test/higher_order_ops/test_inline_asm_elementwise.py (modified, +214/-66)
  • test/run_test.py (modified, +0/-1)
  • torch/_inductor/codegen/triton.py (modified, +16/-1)
  • torch/_inductor/utils.py (modified, +11/-3)
  • torch/testing/_internal/hop_db.py (modified, +8/-0)
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Platforms: rocm

This test was disabled because it is failing on main branch (recent examples).

cc @jeffdaily @sunway513 @jithunnair-amd @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @jerrymannil @xinyazhang @mruberry @chauhang @penguinwu @ydwu4 @bdhirsh @bobrenjc93 @aorenste

extent analysis

TL;DR

The test test_correctness_add_bf16_native in test_inline_asm_elementwise.py needs to be investigated and potentially updated to fix the failure on the main branch.

Guidance

  • Review the recent failure examples on torch-ci.com to understand the nature of the test failure.
  • Investigate the test_correctness_add_bf16_native test in test_inline_asm_elementwise.py to identify potential issues with the test itself or its dependencies.
  • Consider re-enabling the test and running it locally to reproduce and debug the issue.
  • Check if there are any platform-specific issues related to rocm that could be causing the test failure.

Notes

The issue seems to be specific to the rocm platform, so any fixes or workarounds may need to take this into account.

Recommendation

Apply workaround: Investigate and update the failing test to ensure it is compatible with the rocm platform, as the test is currently disabled due to failures on the main branch.

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pytorch - ✅(Solved) Fix DISABLED test_correctness_add_bf16_native (__main__.TestInlineAsmElementwise) [2 pull requests, 1 comments, 2 participants]