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pytorch - ✅(Solved) Fix DISABLED test_hops_compile_backend_aot_eager_inline_asm_elementwise_simple_cuda_float32 (__main__.TestHigherOrderOpsOpInfoCUDA) [2 pull requests, 1 comments, 2 participants]

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pytorch/pytorch#179925•Fetched 2026-04-11 06:11:48
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jithunnair-amdjithunnair-amd
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jithunnair-amdjithunnair-amdpytorch-bot[bot]pytorch-bot[bot]
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Root Cause

This test was disabled because it is failing in CI. See recent examples

PR fix notes

PR #180257: [ROCm] Fix inline_asm_elementwise for ROCm

Description (problem / solution / changelog)

Fixes #179925. Fixes #179927. Fixes #180010. Fixes #179965. Fixes #179982. Fixes #179946.

The inline_asm_elementwise HOP had all assembly hardcoded as PTX and the test file was blocklisted on ROCm. This PR adds AMDGCN equivalents behind torch.version.hip guards so every test case works on both backends. The NVIDIA path is untouched throughout.

Most PTX-to-AMDGCN translations are direct (mov.f32 to v_mov_b32, f/r constraints to v). The fp16/bf16 native cases required a different approach. AMDGCN has no h constraint for 16-bit registers, so we add in f32 and convert down via v_cvt_f16_f32 and v_cvt_pk_bf16_f32.

Two Inductor codegen fixes handle AMDGCN's newline-separated instructions (PTX uses semicolons on one line). In utils.py, multiline format_node() output is split so each line gets the comment prefix. In triton.py, asm literals are double-escaped via repr() to survive two layers of Python string parsing. Both are HIP-guarded.

cc @jeffdaily @sunway513 @jithunnair-amd @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @pragupta @jerrymannil @xinyazhang @voznesenskym @penguinwu @EikanWang @jgong5 @Guobing-Chen @XiaobingSuper @zhuhaozhe @blzheng @wenzhe-nrv @jiayisunx @ipiszy @kadeng @muchulee8 @amjames @chauhang @aakhundov @coconutruben

Changed files

  • test/higher_order_ops/test_inline_asm_elementwise.py (modified, +214/-66)
  • test/run_test.py (modified, +0/-1)
  • torch/_inductor/codegen/triton.py (modified, +16/-1)
  • torch/_inductor/utils.py (modified, +11/-3)
  • torch/testing/_internal/hop_db.py (modified, +8/-0)

PR #180600: [ROCm] Fix inline_asm_elementwise for ROCm

Description (problem / solution / changelog)

Fixes #179925. Fixes #179927. Fixes #180010. Fixes #179965. Fixes #179982. Fixes #179946.

The inline_asm_elementwise HOP had all assembly hardcoded as PTX and the test file was blocklisted on ROCm. This PR adds AMDGCN equivalents behind torch.version.hip guards so every test case works on both backends. The NVIDIA path is untouched throughout.

Most PTX-to-AMDGCN translations are direct (mov.f32 to v_mov_b32, f/r constraints to v). The fp16/bf16 native cases required a different approach. AMDGCN has no h constraint for 16-bit registers, so we add in f32 and convert down via v_cvt_f16_f32 and v_cvt_pk_bf16_f32.

Two Inductor codegen fixes handle AMDGCN's newline-separated instructions (PTX uses semicolons on one line). In utils.py, multiline format_node() output is split so each line gets the comment prefix. In triton.py, asm literals are double-escaped via repr() to survive two layers of Python string parsing. Both are HIP-guarded.

cc @jeffdaily @sunway513 @jithunnair-amd @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @pragupta @jerrymannil @xinyazhang @voznesenskym @penguinwu @EikanWang @jgong5 @Guobing-Chen @XiaobingSuper @zhuhaozhe @blzheng @wenzhe-nrv @jiayisunx @ipiszy @kadeng @muchulee8 @amjames @chauhang @aakhundov @coconutruben

Changed files

  • test/higher_order_ops/test_inline_asm_elementwise.py (modified, +214/-66)
  • test/run_test.py (modified, +0/-1)
  • torch/_inductor/codegen/triton.py (modified, +16/-1)
  • torch/_inductor/utils.py (modified, +11/-3)
  • torch/testing/_internal/hop_db.py (modified, +8/-0)
RAW_BUFFERClick to expand / collapse

Platforms: rocm

This test was disabled because it is failing in CI. See recent examples

cc @jeffdaily @sunway513 @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @pragupta @jerrymannil @xinyazhang @mruberry @chauhang @penguinwu @ydwu4 @bdhirsh @bobrenjc93 @aorenste

extent analysis

TL;DR

The test failure in CI on the rocm platform may be resolved by investigating and addressing the issues identified in the recent examples provided.

Guidance

  • Review the recent examples to understand the nature of the test failures.
  • Collaborate with the listed individuals (e.g., @jeffdaily, @sunway513) to gather more information and insights about the failures.
  • Investigate potential platform-specific issues with rocm that might be contributing to the test failures.
  • Consider re-enabling the test with additional logging or debugging to gather more detailed information about the failures.

Notes

The provided information lacks specific technical details about the test failures, so a more detailed analysis of the recent examples and collaboration with the listed individuals is necessary to determine the root cause.

Recommendation

Apply workaround: Investigate and address the issues identified in the recent examples, as the provided information does not imply a clear upgrade path or fixed version.

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pytorch - ✅(Solved) Fix DISABLED test_hops_compile_backend_aot_eager_inline_asm_elementwise_simple_cuda_float32 (__main__.TestHigherOrderOpsOpInfoCUDA) [2 pull requests, 1 comments, 2 participants]