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pytorch - ✅(Solved) Fix DISABLED test_pre_dispatch_export_inline_asm_elementwise_simple_cuda_float32 (__main__.TestHOPCUDA) [2 pull requests, 1 comments, 2 participants]

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pytorch/pytorch#179965•Fetched 2026-04-11 06:10:57
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praguptapragupta
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praguptapraguptapytorch-bot[bot]pytorch-bot[bot]
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Root Cause

This test was disabled because it is failing on main branch (recent examples).

Fix Action

Fix / Workaround

This test was disabled because it is failing on main branch (recent examples).

PR fix notes

PR #180257: [ROCm] Fix inline_asm_elementwise for ROCm

Description (problem / solution / changelog)

Fixes #179925. Fixes #179927. Fixes #180010. Fixes #179965. Fixes #179982. Fixes #179946.

The inline_asm_elementwise HOP had all assembly hardcoded as PTX and the test file was blocklisted on ROCm. This PR adds AMDGCN equivalents behind torch.version.hip guards so every test case works on both backends. The NVIDIA path is untouched throughout.

Most PTX-to-AMDGCN translations are direct (mov.f32 to v_mov_b32, f/r constraints to v). The fp16/bf16 native cases required a different approach. AMDGCN has no h constraint for 16-bit registers, so we add in f32 and convert down via v_cvt_f16_f32 and v_cvt_pk_bf16_f32.

Two Inductor codegen fixes handle AMDGCN's newline-separated instructions (PTX uses semicolons on one line). In utils.py, multiline format_node() output is split so each line gets the comment prefix. In triton.py, asm literals are double-escaped via repr() to survive two layers of Python string parsing. Both are HIP-guarded.

cc @jeffdaily @sunway513 @jithunnair-amd @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @pragupta @jerrymannil @xinyazhang @voznesenskym @penguinwu @EikanWang @jgong5 @Guobing-Chen @XiaobingSuper @zhuhaozhe @blzheng @wenzhe-nrv @jiayisunx @ipiszy @kadeng @muchulee8 @amjames @chauhang @aakhundov @coconutruben

Changed files

  • test/higher_order_ops/test_inline_asm_elementwise.py (modified, +214/-66)
  • test/run_test.py (modified, +0/-1)
  • torch/_inductor/codegen/triton.py (modified, +16/-1)
  • torch/_inductor/utils.py (modified, +11/-3)
  • torch/testing/_internal/hop_db.py (modified, +8/-0)

PR #180600: [ROCm] Fix inline_asm_elementwise for ROCm

Description (problem / solution / changelog)

Fixes #179925. Fixes #179927. Fixes #180010. Fixes #179965. Fixes #179982. Fixes #179946.

The inline_asm_elementwise HOP had all assembly hardcoded as PTX and the test file was blocklisted on ROCm. This PR adds AMDGCN equivalents behind torch.version.hip guards so every test case works on both backends. The NVIDIA path is untouched throughout.

Most PTX-to-AMDGCN translations are direct (mov.f32 to v_mov_b32, f/r constraints to v). The fp16/bf16 native cases required a different approach. AMDGCN has no h constraint for 16-bit registers, so we add in f32 and convert down via v_cvt_f16_f32 and v_cvt_pk_bf16_f32.

Two Inductor codegen fixes handle AMDGCN's newline-separated instructions (PTX uses semicolons on one line). In utils.py, multiline format_node() output is split so each line gets the comment prefix. In triton.py, asm literals are double-escaped via repr() to survive two layers of Python string parsing. Both are HIP-guarded.

cc @jeffdaily @sunway513 @jithunnair-amd @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @pragupta @jerrymannil @xinyazhang @voznesenskym @penguinwu @EikanWang @jgong5 @Guobing-Chen @XiaobingSuper @zhuhaozhe @blzheng @wenzhe-nrv @jiayisunx @ipiszy @kadeng @muchulee8 @amjames @chauhang @aakhundov @coconutruben

Changed files

  • test/higher_order_ops/test_inline_asm_elementwise.py (modified, +214/-66)
  • test/run_test.py (modified, +0/-1)
  • torch/_inductor/codegen/triton.py (modified, +16/-1)
  • torch/_inductor/utils.py (modified, +11/-3)
  • torch/testing/_internal/hop_db.py (modified, +8/-0)
RAW_BUFFERClick to expand / collapse

Platforms: rocm

This test was disabled because it is failing on main branch (recent examples).

cc @jeffdaily @sunway513 @jithunnair-amd @pruthvistony @ROCmSupport @jataylo @hongxiayang @naromero77amd @jerrymannil @xinyazhang @mruberry

extent analysis

TL;DR

  • Re-enable and re-run the disabled test test_pre_dispatch_export_inline_asm_elementwise_simple_cuda_float32 in test_hop.py to assess the current failure status.

Guidance

  • Review the recent failure examples on torch-ci.com to understand the failure patterns.
  • Investigate potential issues related to the ROCm platform, as the test is failing on this specific platform.
  • Consider collaborating with the mentioned individuals (@jeffdaily, @sunway513, etc.) who may have insights into the test or the platform.

Notes

  • The root cause of the test failure is not explicitly stated, so a thorough investigation is required.
  • The issue might be specific to the rocm platform or the test_hop.py test case.

Recommendation

  • Apply workaround: Temporarily skip the failing test or use an alternative test setup to unblock dependent work, while a more permanent fix is being investigated.
  • Reason: The test failure is blocking, and a workaround can help mitigate the issue until the root cause is identified and addressed.

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pytorch - ✅(Solved) Fix DISABLED test_pre_dispatch_export_inline_asm_elementwise_simple_cuda_float32 (__main__.TestHOPCUDA) [2 pull requests, 1 comments, 2 participants]