pytorch - 💡(How to fix) Fix Flash attention backend type not stored in inductor cache, causes silent usage of wrong backend

pytorch2026-05-27 23:59:16

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Fix Action

Fix / Workaround

CPU: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Address sizes: 46 bits physical, 57 bits virtual Byte Order: Little Endian CPU(s): 128 On-line CPU(s) list: 0-127 Vendor ID: GenuineIntel Model name: INTEL(R) XEON(R) PLATINUM 8562Y+ CPU family: 6 Model: 207 Thread(s) per core: 2 Core(s) per socket: 32 Socket(s): 2 Stepping: 2 CPU(s) scaling MHz: 97% CPU max MHz: 4100.0000 CPU min MHz: 800.0000 BogoMIPS: 5600.00 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect user_shstk avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hfi vnmi avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities Virtualization: VT-x L1d cache: 3 MiB (64 instances) L1i cache: 2 MiB (64 instances) L2 cache: 128 MiB (64 instances) L3 cache: 120 MiB (2 instances) NUMA node(s): 2 NUMA node0 CPU(s): 0-31,64-95 NUMA node1 CPU(s): 32-63,96-127 Vulnerability Gather data sampling: Not affected Vulnerability Itlb multihit: Not affected Vulnerability L1tf: Not affected Vulnerability Mds: Not affected Vulnerability Meltdown: Not affected Vulnerability Mmio stale data: Not affected Vulnerability Reg file data sampling: Not affected Vulnerability Retbleed: Not affected Vulnerability Spec rstack overflow: Not affected Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization Vulnerability Spectre v2: Mitigation; Enhanced / Automatic IBRS; IBPB conditional; RSB filling; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S Vulnerability Srbds: Not affected Vulnerability Tsx async abort: Not affected

Code Example

"""Minimal repro: Inductor's FX graph cache key ignores the SDPA backend selection.

A `torch.compile`'d `F.scaled_dot_product_attention` lowers to a backend-specific
aten op (`_scaled_dot_product_flash_attention` vs `_scaled_dot_product_cudnn_attention`),
chosen from the active SDPA backend selection at compile time. But the on-disk FX
graph cache key does NOT include that selection -- neither the
`torch.nn.attention.sdpa_kernel(...)` context manager nor the
`torch.backends.cuda.enable_*_sdp(...)` flags.

So the first process to compile a given graph populates the cache, and later
processes sharing TORCHINDUCTOR_CACHE_DIR get a cache hit and silently reuse that
backend regardless of what they request. Below, one process compiles the graph
under flash, then a second process requesting cuDNN reuses the cached flash
artifact -- you can see it lower to `_scaled_dot_product_flash_attention` despite
asking for cuDNN. Setting TORCHINDUCTOR_FORCE_DISABLE_CACHES=1 makes the second
process correctly lower to cuDNN, confirming the FX graph cache key is the culprit.

We detect the selected backend by capturing Inductor's `output_code` log and
reading the aten op name from the generated wrapper -- this is the compile-time
selection itself, not a heuristic on runtime kernel names. (Note: don't sniff the
profiler's CUDA kernel names for this -- cuDNN's SDPA kernel on sm100 is named
`cudnn_generated_..._flash_fprop_...`, i.e. it contains the substring "flash",
which trips up naive name matching.)

Run:    python compile_sdpa_cache_repro.py
Compare: TORCHINDUCTOR_FORCE_DISABLE_CACHES=1 python compile_sdpa_cache_repro.py
Requires a CUDA GPU with both flash and cuDNN SDPA backends (sm80+).
"""

import io
import logging
import os
import re
import subprocess
import sys
import tempfile

import torch
from torch.nn.attention import SDPBackend, sdpa_kernel


def f(q, k, v):
    return torch.nn.functional.scaled_dot_product_attention(q, k, v)


def worker(backend: str) -> None:
    """Compile `f` under one SDPA backend; print the aten op Inductor selected."""
    bk = {"flash": SDPBackend.FLASH_ATTENTION, "cudnn": SDPBackend.CUDNN_ATTENTION}[backend]

    # Capture Inductor's generated wrapper code so we can read the selected op.
    buf = io.StringIO()
    torch._logging.set_logs(output_code=True)
    logging.getLogger("torch._inductor").addHandler(logging.StreamHandler(buf))

    # Match how a real consumer selects cuDNN: flip the global enable flag AND
    # enter the sdpa_kernel context. (Neither is part of the FX graph cache key.)
    torch.backends.cuda.enable_cudnn_sdp(backend == "cudnn")
    fc = torch.compile(f, dynamic=False)
    q = k = v = torch.randn(2, 8, 1024, 64, device="cuda", dtype=torch.float16)
    with sdpa_kernel(bk):
        fc(q, k, v)
        torch.cuda.synchronize()

    ops = set(re.findall(r"_scaled_dot_product_(\w+?)_attention", buf.getvalue()))
    print(f"OP={ops.pop() if len(ops) == 1 else sorted(ops)}")


def spawn(backend: str, cache_dir: str) -> str:
    """Run a worker in a fresh process sharing `cache_dir`; return the op it lowered to."""
    env = {**os.environ, "TORCHINDUCTOR_CACHE_DIR": cache_dir}
    out = subprocess.run([sys.executable, __file__, backend], env=env, capture_output=True, text=True).stdout
    return next(line[3:] for line in out.splitlines() if line.startswith("OP="))


if __name__ == "__main__":
    if len(sys.argv) > 1:  # worker mode
        worker(sys.argv[1])
        sys.exit()

    print("torch", torch.__version__, "| cuda", torch.version.cuda, "|", torch.cuda.get_device_name())
    print("TORCHINDUCTOR_FORCE_DISABLE_CACHES =", os.environ.get("TORCHINDUCTOR_FORCE_DISABLE_CACHES", "<unset>"))
    with tempfile.TemporaryDirectory() as cache_dir:  # one shared, initially-empty cache
        flash_op = spawn("flash", cache_dir)  # populates the cache
        cudnn_op = spawn("cudnn", cache_dir)  # should lower to cudnn; gets a cache hit instead
    print(f"process 1 requested flash -> lowered to {flash_op}")
    print(f"process 2 requested cudnn -> lowered to {cudnn_op}")
    assert flash_op == "flash", f"expected flash, got {flash_op}"
    if cudnn_op == "flash":
        print("\nBUG: the cuDNN process reused the cached flash artifact. "
              "Rerun with TORCHINDUCTOR_FORCE_DISABLE_CACHES=1 and process 2 correctly lowers to cudnn.")
    else:
        print(f"\nNo bug here: process 2 lowered to {cudnn_op} (cache disabled, or the cache key has been fixed).")

---

kevin@kevin-b200-0:/mnt/clusterstorage/workspace/kevin/ml-monorepo/chadfusion$ python compile_sdpa_cache_repro.py 
torch 2.12.0 | cuda 13.2 | NVIDIA B200
TORCHINDUCTOR_FORCE_DISABLE_CACHES = <unset>
process 1 requested flash -> lowered to flash
process 2 requested cudnn -> lowered to flash

---

Collecting environment information...
PyTorch version: 2.12.0
Is debug build: False
CUDA used to build PyTorch: 13.2
ROCM used to build PyTorch: N/A

OS: Ubuntu 24.04.4 LTS (x86_64)
GCC version: (Ubuntu 13.3.0-6ubuntu2~24.04.1) 13.3.0
Clang version: Could not collect
CMake version: version 4.3.2
Libc version: glibc-2.39

Python version: 3.12.3 (main, Mar 23 2026, 19:04:32) [GCC 13.3.0] (64-bit runtime)
Python platform: Linux-6.8.12-680-6063-coreweave-amd64-f81899c8-x86_64-with-glibc2.39
Is CUDA available: True
CUDA runtime version: 13.2.78
CUDA_MODULE_LOADING set to: 
GPU models and configuration: GPU 0: NVIDIA B200
Nvidia driver version: 595.45.04
cuDNN version: Probably one of the following:
/usr/lib/x86_64-linux-gnu/libcudnn.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_adv.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_cnn.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_engines_precompiled.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_engines_runtime_compiled.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_graph.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_heuristic.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_ops.so.9.20.0
Is XPU available: False
HIP runtime version: N/A
MIOpen runtime version: N/A
Is XNNPACK available: True
Caching allocator config: N/A

CPU:
Architecture:                         x86_64
CPU op-mode(s):                       32-bit, 64-bit
Address sizes:                        46 bits physical, 57 bits virtual
Byte Order:                           Little Endian
CPU(s):                               128
On-line CPU(s) list:                  0-127
Vendor ID:                            GenuineIntel
Model name:                           INTEL(R) XEON(R) PLATINUM 8562Y+
CPU family:                           6
Model:                                207
Thread(s) per core:                   2
Core(s) per socket:                   32
Socket(s):                            2
Stepping:                             2
CPU(s) scaling MHz:                   97%
CPU max MHz:                          4100.0000
CPU min MHz:                          800.0000
BogoMIPS:                             5600.00
Flags:                                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect user_shstk avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hfi vnmi avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
Virtualization:                       VT-x
L1d cache:                            3 MiB (64 instances)
L1i cache:                            2 MiB (64 instances)
L2 cache:                             128 MiB (64 instances)
L3 cache:                             120 MiB (2 instances)
NUMA node(s):                         2
NUMA node0 CPU(s):                    0-31,64-95
NUMA node1 CPU(s):                    32-63,96-127
Vulnerability Gather data sampling:   Not affected
Vulnerability Itlb multihit:          Not affected
Vulnerability L1tf:                   Not affected
Vulnerability Mds:                    Not affected
Vulnerability Meltdown:               Not affected
Vulnerability Mmio stale data:        Not affected
Vulnerability Reg file data sampling: Not affected
Vulnerability Retbleed:               Not affected
Vulnerability Spec rstack overflow:   Not affected
Vulnerability Spec store bypass:      Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1:             Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:             Mitigation; Enhanced / Automatic IBRS; IBPB conditional; RSB filling; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S
Vulnerability Srbds:                  Not affected
Vulnerability Tsx async abort:        Not affected

Versions of relevant libraries:
[pip3] mypy_extensions==1.1.0
[pip3] numpy==1.26.4
[pip3] onnx==1.21.0
[pip3] onnx-ir==0.2.1
[pip3] onnxscript==0.7.0
[pip3] torch==2.12.0
[pip3] torch_c_dlpack_ext==0.1.5
[pip3] torchaudio==2.11.0
[pip3] torchdata==0.11.0
[pip3] torchdiffeq==0.2.5
[pip3] torchsde==0.2.6
[pip3] torchvision==0.27.0
[pip3] triton==3.7.0+gitb4e20bbe
[pip3] welford-torch==0.2.5
[conda] Could not collect

RAW_BUFFERClick to expand / collapse

🐛 Describe the bug

"""Minimal repro: Inductor's FX graph cache key ignores the SDPA backend selection.

A `torch.compile`'d `F.scaled_dot_product_attention` lowers to a backend-specific
aten op (`_scaled_dot_product_flash_attention` vs `_scaled_dot_product_cudnn_attention`),
chosen from the active SDPA backend selection at compile time. But the on-disk FX
graph cache key does NOT include that selection -- neither the
`torch.nn.attention.sdpa_kernel(...)` context manager nor the
`torch.backends.cuda.enable_*_sdp(...)` flags.

So the first process to compile a given graph populates the cache, and later
processes sharing TORCHINDUCTOR_CACHE_DIR get a cache hit and silently reuse that
backend regardless of what they request. Below, one process compiles the graph
under flash, then a second process requesting cuDNN reuses the cached flash
artifact -- you can see it lower to `_scaled_dot_product_flash_attention` despite
asking for cuDNN. Setting TORCHINDUCTOR_FORCE_DISABLE_CACHES=1 makes the second
process correctly lower to cuDNN, confirming the FX graph cache key is the culprit.

We detect the selected backend by capturing Inductor's `output_code` log and
reading the aten op name from the generated wrapper -- this is the compile-time
selection itself, not a heuristic on runtime kernel names. (Note: don't sniff the
profiler's CUDA kernel names for this -- cuDNN's SDPA kernel on sm100 is named
`cudnn_generated_..._flash_fprop_...`, i.e. it contains the substring "flash",
which trips up naive name matching.)

Run:    python compile_sdpa_cache_repro.py
Compare: TORCHINDUCTOR_FORCE_DISABLE_CACHES=1 python compile_sdpa_cache_repro.py
Requires a CUDA GPU with both flash and cuDNN SDPA backends (sm80+).
"""

import io
import logging
import os
import re
import subprocess
import sys
import tempfile

import torch
from torch.nn.attention import SDPBackend, sdpa_kernel


def f(q, k, v):
    return torch.nn.functional.scaled_dot_product_attention(q, k, v)


def worker(backend: str) -> None:
    """Compile `f` under one SDPA backend; print the aten op Inductor selected."""
    bk = {"flash": SDPBackend.FLASH_ATTENTION, "cudnn": SDPBackend.CUDNN_ATTENTION}[backend]

    # Capture Inductor's generated wrapper code so we can read the selected op.
    buf = io.StringIO()
    torch._logging.set_logs(output_code=True)
    logging.getLogger("torch._inductor").addHandler(logging.StreamHandler(buf))

    # Match how a real consumer selects cuDNN: flip the global enable flag AND
    # enter the sdpa_kernel context. (Neither is part of the FX graph cache key.)
    torch.backends.cuda.enable_cudnn_sdp(backend == "cudnn")
    fc = torch.compile(f, dynamic=False)
    q = k = v = torch.randn(2, 8, 1024, 64, device="cuda", dtype=torch.float16)
    with sdpa_kernel(bk):
        fc(q, k, v)
        torch.cuda.synchronize()

    ops = set(re.findall(r"_scaled_dot_product_(\w+?)_attention", buf.getvalue()))
    print(f"OP={ops.pop() if len(ops) == 1 else sorted(ops)}")


def spawn(backend: str, cache_dir: str) -> str:
    """Run a worker in a fresh process sharing `cache_dir`; return the op it lowered to."""
    env = {**os.environ, "TORCHINDUCTOR_CACHE_DIR": cache_dir}
    out = subprocess.run([sys.executable, __file__, backend], env=env, capture_output=True, text=True).stdout
    return next(line[3:] for line in out.splitlines() if line.startswith("OP="))


if __name__ == "__main__":
    if len(sys.argv) > 1:  # worker mode
        worker(sys.argv[1])
        sys.exit()

    print("torch", torch.__version__, "| cuda", torch.version.cuda, "|", torch.cuda.get_device_name())
    print("TORCHINDUCTOR_FORCE_DISABLE_CACHES =", os.environ.get("TORCHINDUCTOR_FORCE_DISABLE_CACHES", "<unset>"))
    with tempfile.TemporaryDirectory() as cache_dir:  # one shared, initially-empty cache
        flash_op = spawn("flash", cache_dir)  # populates the cache
        cudnn_op = spawn("cudnn", cache_dir)  # should lower to cudnn; gets a cache hit instead
    print(f"process 1 requested flash -> lowered to {flash_op}")
    print(f"process 2 requested cudnn -> lowered to {cudnn_op}")
    assert flash_op == "flash", f"expected flash, got {flash_op}"
    if cudnn_op == "flash":
        print("\nBUG: the cuDNN process reused the cached flash artifact. "
              "Rerun with TORCHINDUCTOR_FORCE_DISABLE_CACHES=1 and process 2 correctly lowers to cudnn.")
    else:
        print(f"\nNo bug here: process 2 lowered to {cudnn_op} (cache disabled, or the cache key has been fixed).")

Error logs

kevin@kevin-b200-0:/mnt/clusterstorage/workspace/kevin/ml-monorepo/chadfusion$ python compile_sdpa_cache_repro.py 
torch 2.12.0 | cuda 13.2 | NVIDIA B200
TORCHINDUCTOR_FORCE_DISABLE_CACHES = <unset>
process 1 requested flash -> lowered to flash
process 2 requested cudnn -> lowered to flash

Versions

Collecting environment information...
PyTorch version: 2.12.0
Is debug build: False
CUDA used to build PyTorch: 13.2
ROCM used to build PyTorch: N/A

OS: Ubuntu 24.04.4 LTS (x86_64)
GCC version: (Ubuntu 13.3.0-6ubuntu2~24.04.1) 13.3.0
Clang version: Could not collect
CMake version: version 4.3.2
Libc version: glibc-2.39

Python version: 3.12.3 (main, Mar 23 2026, 19:04:32) [GCC 13.3.0] (64-bit runtime)
Python platform: Linux-6.8.12-680-6063-coreweave-amd64-f81899c8-x86_64-with-glibc2.39
Is CUDA available: True
CUDA runtime version: 13.2.78
CUDA_MODULE_LOADING set to: 
GPU models and configuration: GPU 0: NVIDIA B200
Nvidia driver version: 595.45.04
cuDNN version: Probably one of the following:
/usr/lib/x86_64-linux-gnu/libcudnn.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_adv.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_cnn.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_engines_precompiled.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_engines_runtime_compiled.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_graph.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_heuristic.so.9.20.0
/usr/lib/x86_64-linux-gnu/libcudnn_ops.so.9.20.0
Is XPU available: False
HIP runtime version: N/A
MIOpen runtime version: N/A
Is XNNPACK available: True
Caching allocator config: N/A

CPU:
Architecture:                         x86_64
CPU op-mode(s):                       32-bit, 64-bit
Address sizes:                        46 bits physical, 57 bits virtual
Byte Order:                           Little Endian
CPU(s):                               128
On-line CPU(s) list:                  0-127
Vendor ID:                            GenuineIntel
Model name:                           INTEL(R) XEON(R) PLATINUM 8562Y+
CPU family:                           6
Model:                                207
Thread(s) per core:                   2
Core(s) per socket:                   32
Socket(s):                            2
Stepping:                             2
CPU(s) scaling MHz:                   97%
CPU max MHz:                          4100.0000
CPU min MHz:                          800.0000
BogoMIPS:                             5600.00
Flags:                                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect user_shstk avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hfi vnmi avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
Virtualization:                       VT-x
L1d cache:                            3 MiB (64 instances)
L1i cache:                            2 MiB (64 instances)
L2 cache:                             128 MiB (64 instances)
L3 cache:                             120 MiB (2 instances)
NUMA node(s):                         2
NUMA node0 CPU(s):                    0-31,64-95
NUMA node1 CPU(s):                    32-63,96-127
Vulnerability Gather data sampling:   Not affected
Vulnerability Itlb multihit:          Not affected
Vulnerability L1tf:                   Not affected
Vulnerability Mds:                    Not affected
Vulnerability Meltdown:               Not affected
Vulnerability Mmio stale data:        Not affected
Vulnerability Reg file data sampling: Not affected
Vulnerability Retbleed:               Not affected
Vulnerability Spec rstack overflow:   Not affected
Vulnerability Spec store bypass:      Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1:             Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:             Mitigation; Enhanced / Automatic IBRS; IBPB conditional; RSB filling; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S
Vulnerability Srbds:                  Not affected
Vulnerability Tsx async abort:        Not affected

Versions of relevant libraries:
[pip3] mypy_extensions==1.1.0
[pip3] numpy==1.26.4
[pip3] onnx==1.21.0
[pip3] onnx-ir==0.2.1
[pip3] onnxscript==0.7.0
[pip3] torch==2.12.0
[pip3] torch_c_dlpack_ext==0.1.5
[pip3] torchaudio==2.11.0
[pip3] torchdata==0.11.0
[pip3] torchdiffeq==0.2.5
[pip3] torchsde==0.2.6
[pip3] torchvision==0.27.0
[pip3] triton==3.7.0+gitb4e20bbe
[pip3] welford-torch==0.2.5
[conda] Could not collect

cc @chauhang @penguinwu @voznesenskym @EikanWang @jgong5 @Guobing-Chen @XiaobingSuper @zhuhaozhe @blzheng @wenzhe-nrv @jiayisunx @ipiszy @kadeng @muchulee8 @amjames @aakhundov @coconutruben @jataylo @drisspg @liangel-02 @howardzhang-cv

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pytorch - 💡(How to fix) Fix Flash attention backend type not stored in inductor cache, causes silent usage of wrong backend

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