vllm - ✅(Solved) Fix [Bug]: Shared Expert output is incorrect under Sequence Parallel MoE (EP + TP > 1 + DP > 1) for Qwen3.5 MoE models [2 pull requests, 1 comments, 2 participants]

jQizhang · 2026-03-23T06:26:45Z

[vllm] PR 5: add Qwen3.5-9B megatron nightly test - Repository: zpqiu/NeMo-RL - Author: jQizhang - State: closed | merged: True - Link: https://github.com/zpqi… # PR #5: add Qwen3.5-9B megatron nightly test - Repository: zpqiu/NeMo-RL - Author: jQizhang - State: closed | merged: True - Link: https://github.com/zpqiu/NeMo-RL/pull/5 ## Description (problem / solution / changelog) ## Summary - Add Qwen3.5-9B Megatron GRPO nightly test config (`grpo-qwen3.5-9b-1n8g-megatron.yaml`), running on 1 node x 8 GPUs with TP=4 - Add Qwen3.5-397B-A17B Megatron GRPO training config (`grpo-qwen3.5-397ba17b-32n8g-megatron.yaml`), running on 32 nodes x 8 GPUs with TP=8, PP=8, EP=32, vLLM generation with TP=16 EP=64 - Register the test in `nightly.txt` - Register test in `disabled.txt` due to known vLLM bug: https://github.com/vllm-project/vllm/issues/37856 ## Changed files - `examples/configs/recipes/llm/grpo-qwen3.5-397ba17b-32n8g-megatron.yaml` (added, +159/-0) - `examples/configs/recipes/llm/grpo-qwen3.5-9b-1n8g-megatron.yaml` (added, +48/-0) - `tests/test_suites/disabled.txt` (modified, +4/-1) - `tests/test_suites/llm/grpo-qwen3.5-397ba17b-32n8g-megatron.sh` (added, +42/-0) - `tests/test_suites/llm/grpo-qwen3.5-9b-1n8g-megatron.sh` (added, +42/-0) - `tests/test_suites/nightly.txt` (modified, +3/-0) --- # PR #2151: feat: add Qwen3.5 & GLM-4.7-Flash model support - Repository: NVIDIA-NeMo/RL - Author: zpqiu - State: closed | merged: True - Link: https://github.com/NVIDIA-NeMo/RL/pull/2151 ## Description (problem / solution / changelog) ## Summary - Add Qwen3.5 architecture support (Qwen3_5ForConditionalGeneration, Qwen3_5MoeForConditionalGeneration) to vLLM conditional generation handling - Freeze visual encoder for text-only training of VLM-capable models to prevent optimizer state key mismatch on checkpoint resume - Copy chat_template from tokenizer to processor for models whose processor lacks its own template (e.g. Qwen3.5) - Make enable_prefix_caching configurable via vllm_cfg - Clear multimodal processor cache on sleep to prevent sender/receiver cache desync (sync and async paths) ## Offline Experiments https://wandb.ai/ys_fishcool-nvidia/nemorl-qwen35?nw=nwuserys_fishcool | Model | Backend | GRPO Validated? | Comments| | -- | -- | -- | --| | Qwen3.5-2B/4B | Automodel | Yes | | | Qwen3.5-35B-A3B | Automodel | Yes | | | Qwen3.5-35B-A3B (VLM task) | Automodel | Yes | | | Qwen3.5-397B-A17B | Automodel | No | Need Automodel PP| | Qwen3.5-2B/4B | MCore | Yes with issue | Will work after next Megatron-Bridge verion bump, Related issue: https://github.com/NVIDIA-NeMo/Megatron-Bridge/issues/3112 | | Qwen3.5-9B | MCore | Yes | | Qwen3.5-35B-A3B | MCore | Yes | | Qwen3.5-35B-A3B (VLM task) | MCore | Yes | | Qwen3.5-397B-A17B | MCore | Yes | Problem only happens when vllm has EP enabled + TP > 1 + DP > 1. Garbled output is generated, see issue: https://github.com/vllm-project/vllm/issues/37856 | | GLM-4.7-Flash | Automodel | Yes | | ## Known Issues - By default, NeMo Automodel does not install the FLA dependency. To use CP on the DTensor V2 path, you need to install it separately with `pip install flash-linear-attention`. - In our offline Qwen3.5 experiments, we occasionally encounter this known vLLM issue, and it occurs more frequently in multimodal training tasks. https://github.com/vllm-project/vllm/issues/36237 - Sequence packing on DTensor V2 path may have this issue: https://github.com/NVIDIA-NeMo/RL/issues/2105 - Training small Qwen3.5 dense models (2B/4B) on the Megatron-Bridge backend may have this issue: https://github.com/NVIDIA-NeMo/Megatron-Bridge/issues/3112 ## Changed files - `README.md` (modified, +4/-0) - `docs/about/model-support.md` (modified, +3/-2) - `examples/configs/recipes/llm/grpo-glm47-flash-4n8g-automodel.yaml` (added, +77/-0) - `examples/configs/recipes/llm/grpo-qwen2.5-7b-instruct-4n4g-fsdp2tp2.v3.yaml` (modified, +37/-2) - `examples/configs/recipes/llm/grpo-qwen2.5-7b-instruct-4n8g-fsdp2tp4.v3.yaml` (removed, +0/-52) - `examples/configs/recipes/llm/grpo-qwen3.5-35ba3b-2n8g-automodel-ep16.yaml` (added, +40/-0) - `examples/configs/recipes/llm/grpo-qwen3.5-35ba3b-2n8g-megatron-ep16.yaml` (added, +31/-0) - `examples/configs/recipes/llm/grpo-qwen3.5-35ba3b-dapo-4n8g-automodel.yaml` (added, +84/-0) - `examples/configs/recipes/llm/grpo-qwen3.5-397ba17b-32n8g-megatron.yaml` (added, +81/-0) - `examples/configs/recipes/llm/grpo-qwen3.5-9b-1n8g-megatron.yaml` (added, +31/-0) - `examples/configs/recipes/vlm/vlm_grpo-qwen3.5-35ba3b-geo3k-2n8g-automodel-ep16.yaml` (added, +57/-0) - `examples/configs/recipes/vlm/vlm_grpo-qwen3.5-35ba3b-geo3k-2n8g-megatron-ep16.yaml` (added, +59/-0) - `nemo_rl/algorithms/utils.py` (modified, +6/-0) - `nemo_rl/models/automodel/setup.py` (modified, +29/-0) - `nemo_rl/models/generation/vllm/vllm_worker.py` (modified, +33/-4) - `nemo_rl/models/generation/vllm/vllm_worker_async.py` (modified, +6/-0) - `nemo_rl/models/policy/utils.py` (modified, +13/-0) - `tests/test_suites/disabled.txt

vllm2026-03-23 06:26:45

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vllm-project/vllm#37856•Fetched 2026-04-08 01:17:32

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Author

jQizhang

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Error Message

NCCL_DEBUG=WARN

Root Cause

When use_sequence_parallel_moe is True (triggered by EP enabled + TP > 1 + DP > 1), Qwen3NextSparseMoeBlock.forward() chunks the input via sequence_parallel_chunk, so each TP rank processes only N/TP different tokens.

This is correct for routed experts — the EP all-to-all mechanism handles chunked tokens properly.

But it breaks the shared expert. The shared expert MLP uses TP-sharded weights (ColumnParallelLinear + RowParallelLinear with reduce_results=False). TP requires all ranks to process the same tokens so that partial sums from different weight shards can be correctly combined. After chunking, each rank holds different tokens, so:

Rank 0: tokens[0..N/8)    × weight_shard_0 → partial for tokens 0..N/8
Rank 1: tokens[N/8..2N/8) × weight_shard_1 → partial for tokens N/8..2N/8
...

Neither all_reduce (mixes partial sums of different tokens) nor all_gather (what the code currently does — leaves each token with only 1/TP of its correct value) can produce the correct result. The net effect is that each token's shared expert output is scaled down by 1/TP.

Fix Action

Fix / Workaround

============================== CPU Info

Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Address sizes: 46 bits physical, 57 bits virtual Byte Order: Little Endian CPU(s): 128 On-line CPU(s) list: 0-127 Vendor ID: GenuineIntel Model name: Intel(R) Xeon(R) Platinum 8462Y+ CPU family: 6 Model: 143 Thread(s) per core: 2 Core(s) per socket: 32 Socket(s): 2 Stepping: 8 Frequency boost: enabled CPU(s) scaling MHz: 114% CPU max MHz: 2801.0000 CPU min MHz: 800.0000 BogoMIPS: 5600.00 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities Virtualization: VT-x L1d cache: 3 MiB (64 instances) L1i cache: 2 MiB (64 instances) L2 cache: 128 MiB (64 instances) L3 cache: 120 MiB (2 instances) NUMA node(s): 2 NUMA node0 CPU(s): 0-31,64-95 NUMA node1 CPU(s): 32-63,96-127 Vulnerability Gather data sampling: Not affected Vulnerability Itlb multihit: Not affected Vulnerability L1tf: Not affected Vulnerability Mds: Not affected Vulnerability Meltdown: Not affected Vulnerability Mmio stale data: Not affected Vulnerability Reg file data sampling: Not affected Vulnerability Retbleed: Not affected Vulnerability Spec rstack overflow: Not affected Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization Vulnerability Spectre v2: Mitigation; Enhanced / Automatic IBRS; IBPB conditional; RSB filling; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S Vulnerability Srbds: Not affected Vulnerability Tsx async abort: Not affected

PR fix notes

PR #5: add Qwen3.5-9B megatron nightly test

Repository: zpqiu/NeMo-RL
Author: jQizhang
State: closed | merged: True
Link: https://github.com/zpqiu/NeMo-RL/pull/5

Description (problem / solution / changelog)

Summary

Add Qwen3.5-9B Megatron GRPO nightly test config (grpo-qwen3.5-9b-1n8g-megatron.yaml), running on 1 node x 8 GPUs with TP=4
Add Qwen3.5-397B-A17B Megatron GRPO training config (grpo-qwen3.5-397ba17b-32n8g-megatron.yaml), running on 32 nodes x 8 GPUs with TP=8, PP=8, EP=32, vLLM generation with TP=16 EP=64
Register the test in nightly.txt
Register test in disabled.txt due to known vLLM bug: https://github.com/vllm-project/vllm/issues/37856

Changed files

examples/configs/recipes/llm/grpo-qwen3.5-397ba17b-32n8g-megatron.yaml (added, +159/-0)
examples/configs/recipes/llm/grpo-qwen3.5-9b-1n8g-megatron.yaml (added, +48/-0)
tests/test_suites/disabled.txt (modified, +4/-1)
tests/test_suites/llm/grpo-qwen3.5-397ba17b-32n8g-megatron.sh (added, +42/-0)
tests/test_suites/llm/grpo-qwen3.5-9b-1n8g-megatron.sh (added, +42/-0)
tests/test_suites/nightly.txt (modified, +3/-0)

PR #2151: feat: add Qwen3.5 & GLM-4.7-Flash model support

Repository: NVIDIA-NeMo/RL
Author: zpqiu
State: closed | merged: True
Link: https://github.com/NVIDIA-NeMo/RL/pull/2151

Description (problem / solution / changelog)

Summary

Add Qwen3.5 architecture support (Qwen3_5ForConditionalGeneration, Qwen3_5MoeForConditionalGeneration) to vLLM conditional generation handling
Freeze visual encoder for text-only training of VLM-capable models to prevent optimizer state key mismatch on checkpoint resume
Copy chat_template from tokenizer to processor for models whose processor lacks its own template (e.g. Qwen3.5)
Make enable_prefix_caching configurable via vllm_cfg
Clear multimodal processor cache on sleep to prevent sender/receiver cache desync (sync and async paths)

Offline Experiments

https://wandb.ai/ys_fishcool-nvidia/nemorl-qwen35?nw=nwuserys_fishcool

Model	Backend	GRPO Validated?	Comments
Qwen3.5-2B/4B	Automodel	Yes
Qwen3.5-35B-A3B	Automodel	Yes
Qwen3.5-35B-A3B (VLM task)	Automodel	Yes
Qwen3.5-397B-A17B	Automodel	No	Need Automodel PP
Qwen3.5-2B/4B	MCore	Yes with issue	Will work after next Megatron-Bridge verion bump, Related issue: https://github.com/NVIDIA-NeMo/Megatron-Bridge/issues/3112
Qwen3.5-9B	MCore	Yes
Qwen3.5-35B-A3B	MCore	Yes
Qwen3.5-35B-A3B (VLM task)	MCore	Yes
Qwen3.5-397B-A17B	MCore	Yes	Problem only happens when vllm has EP enabled + TP > 1 + DP > 1. Garbled output is generated, see issue: https://github.com/vllm-project/vllm/issues/37856
GLM-4.7-Flash	Automodel	Yes

Known Issues

By default, NeMo Automodel does not install the FLA dependency. To use CP on the DTensor V2 path, you need to install it separately with pip install flash-linear-attention.
In our offline Qwen3.5 experiments, we occasionally encounter this known vLLM issue, and it occurs more frequently in multimodal training tasks. https://github.com/vllm-project/vllm/issues/36237
Sequence packing on DTensor V2 path may have this issue: https://github.com/NVIDIA-NeMo/RL/issues/2105
Training small Qwen3.5 dense models (2B/4B) on the Megatron-Bridge backend may have this issue: https://github.com/NVIDIA-NeMo/Megatron-Bridge/issues/3112

Changed files

README.md (modified, +4/-0)
docs/about/model-support.md (modified, +3/-2)
examples/configs/recipes/llm/grpo-glm47-flash-4n8g-automodel.yaml (added, +77/-0)
examples/configs/recipes/llm/grpo-qwen2.5-7b-instruct-4n4g-fsdp2tp2.v3.yaml (modified, +37/-2)
examples/configs/recipes/llm/grpo-qwen2.5-7b-instruct-4n8g-fsdp2tp4.v3.yaml (removed, +0/-52)
examples/configs/recipes/llm/grpo-qwen3.5-35ba3b-2n8g-automodel-ep16.yaml (added, +40/-0)
examples/configs/recipes/llm/grpo-qwen3.5-35ba3b-2n8g-megatron-ep16.yaml (added, +31/-0)
examples/configs/recipes/llm/grpo-qwen3.5-35ba3b-dapo-4n8g-automodel.yaml (added, +84/-0)
examples/configs/recipes/llm/grpo-qwen3.5-397ba17b-32n8g-megatron.yaml (added, +81/-0)
examples/configs/recipes/llm/grpo-qwen3.5-9b-1n8g-megatron.yaml (added, +31/-0)
examples/configs/recipes/vlm/vlm_grpo-qwen3.5-35ba3b-geo3k-2n8g-automodel-ep16.yaml (added, +57/-0)
examples/configs/recipes/vlm/vlm_grpo-qwen3.5-35ba3b-geo3k-2n8g-megatron-ep16.yaml (added, +59/-0)
nemo_rl/algorithms/utils.py (modified, +6/-0)
nemo_rl/models/automodel/setup.py (modified, +29/-0)
nemo_rl/models/generation/vllm/vllm_worker.py (modified, +33/-4)
nemo_rl/models/generation/vllm/vllm_worker_async.py (modified, +6/-0)
nemo_rl/models/policy/utils.py (modified, +13/-0)
tests/test_suites/disabled.txt (modified, +6/-0)
tests/test_suites/llm/grpo-glm47-flash-4n8g-automodel.sh (renamed, +5/-3)
tests/test_suites/llm/grpo-qwen3.5-35ba3b-2n8g-automodel-ep16.sh (added, +42/-0)
tests/test_suites/llm/grpo-qwen3.5-35ba3b-2n8g-megatron-ep16.sh (added, +42/-0)
tests/test_suites/llm/grpo-qwen3.5-35ba3b-dapo-4n8g-automodel.sh (added, +45/-0)
tests/test_suites/llm/grpo-qwen3.5-397ba17b-32n8g-megatron.sh (added, +42/-0)
tests/test_suites/llm/grpo-qwen3.5-9b-1n8g-megatron.sh (added, +42/-0)
tests/test_suites/nightly.txt (modified, +12/-3)
tests/test_suites/release.txt (modified, +6/-0)
tests/test_suites/vlm/vlm_grpo-qwen3.5-35ba3b-geo3k-2n8g-automodel-ep16.sh (added, +41/-0)
tests/test_suites/vlm/vlm_grpo-qwen3.5-35ba3b-geo3k-2n8g-megatron-ep16.sh (added, +41/-0)
tests/unit/test_recipes_and_test_suites.py (modified, +3/-3)

Code Example

==============================
        System Info
==============================
OS                           : Ubuntu 24.04.2 LTS (x86_64)
GCC version                  : (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0
Clang version                : Could not collect
CMake version                : version 3.31.1
Libc version                 : glibc-2.39

==============================
       PyTorch Info
==============================
PyTorch version              : 2.10.0+cu129
Is debug build               : False
CUDA used to build PyTorch   : 12.9
ROCM used to build PyTorch   : N/A

==============================
      Python Environment
==============================
Python version               : 3.12.12 (main, Oct 28 2025, 12:10:49) [Clang 20.1.4 ] (64-bit runtime)
Python platform              : Linux-5.15.0-1063-nvidia-x86_64-with-glibc2.39

==============================
       CUDA / GPU Info
==============================
Is CUDA available            : True
CUDA runtime version         : 12.9.41
CUDA_MODULE_LOADING set to   : 
GPU models and configuration : 
GPU 0: NVIDIA H100 80GB HBM3
GPU 1: NVIDIA H100 80GB HBM3
GPU 2: NVIDIA H100 80GB HBM3
GPU 3: NVIDIA H100 80GB HBM3
GPU 4: NVIDIA H100 80GB HBM3
GPU 5: NVIDIA H100 80GB HBM3
GPU 6: NVIDIA H100 80GB HBM3
GPU 7: NVIDIA H100 80GB HBM3

Nvidia driver version        : 535.216.03
cuDNN version                : Probably one of the following:
/usr/lib/x86_64-linux-gnu/libcudnn.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_adv.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_cnn.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_engines_precompiled.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_engines_runtime_compiled.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_graph.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_heuristic.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_ops.so.9.10.1
HIP runtime version          : N/A
MIOpen runtime version       : N/A
Is XNNPACK available         : True

==============================
          CPU Info
==============================
Architecture:                         x86_64
CPU op-mode(s):                       32-bit, 64-bit
Address sizes:                        46 bits physical, 57 bits virtual
Byte Order:                           Little Endian
CPU(s):                               128
On-line CPU(s) list:                  0-127
Vendor ID:                            GenuineIntel
Model name:                           Intel(R) Xeon(R) Platinum 8462Y+
CPU family:                           6
Model:                                143
Thread(s) per core:                   2
Core(s) per socket:                   32
Socket(s):                            2
Stepping:                             8
Frequency boost:                      enabled
CPU(s) scaling MHz:                   114%
CPU max MHz:                          2801.0000
CPU min MHz:                          800.0000
BogoMIPS:                             5600.00
Flags:                                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
Virtualization:                       VT-x
L1d cache:                            3 MiB (64 instances)
L1i cache:                            2 MiB (64 instances)
L2 cache:                             128 MiB (64 instances)
L3 cache:                             120 MiB (2 instances)
NUMA node(s):                         2
NUMA node0 CPU(s):                    0-31,64-95
NUMA node1 CPU(s):                    32-63,96-127
Vulnerability Gather data sampling:   Not affected
Vulnerability Itlb multihit:          Not affected
Vulnerability L1tf:                   Not affected
Vulnerability Mds:                    Not affected
Vulnerability Meltdown:               Not affected
Vulnerability Mmio stale data:        Not affected
Vulnerability Reg file data sampling: Not affected
Vulnerability Retbleed:               Not affected
Vulnerability Spec rstack overflow:   Not affected
Vulnerability Spec store bypass:      Mitigation; Speculative Store Bypass disabled via prctl and seccomp
Vulnerability Spectre v1:             Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:             Mitigation; Enhanced / Automatic IBRS; IBPB conditional; RSB filling; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S
Vulnerability Srbds:                  Not affected
Vulnerability Tsx async abort:        Not affected

==============================
Versions of relevant libraries
==============================
[pip3] flashinfer-python==0.6.4
[pip3] nccl4py==0.1.1
[pip3] numpy==2.2.6
[pip3] nvidia-cublas-cu12==12.9.1.4
[pip3] nvidia-cuda-cupti-cu12==12.9.79
[pip3] nvidia-cuda-nvrtc-cu12==12.9.86
[pip3] nvidia-cuda-runtime-cu12==12.9.79
[pip3] nvidia-cudnn-cu12==9.19.0.56
[pip3] nvidia-cudnn-frontend==1.18.0
[pip3] nvidia-cufft-cu12==11.4.1.4
[pip3] nvidia-cufile-cu12==1.14.1.1
[pip3] nvidia-curand-cu12==10.3.10.19
[pip3] nvidia-cusolver-cu12==11.7.5.82
[pip3] nvidia-cusparse-cu12==12.5.10.65
[pip3] nvidia-cusparselt-cu12==0.7.1
[pip3] nvidia-cutlass-dsl==4.4.1
[pip3] nvidia-cutlass-dsl-libs-base==4.4.1
[pip3] nvidia-ml-py==13.590.48
[pip3] nvidia-nccl-cu12==2.27.5
[pip3] nvidia-nvjitlink-cu12==12.9.86
[pip3] nvidia-nvshmem-cu12==3.4.5
[pip3] nvidia-nvtx-cu12==12.9.79
[pip3] nvidia-resiliency-ext==0.5.0
[pip3] pyzmq==27.1.0
[pip3] torch==2.10.0+cu129
[pip3] torch_c_dlpack_ext==0.1.5
[pip3] torchaudio==2.9.0
[pip3] torchdata==0.11.0
[pip3] torchvision==0.25.0+cu129
[pip3] transformers==5.3.0.dev0
[pip3] triton==3.6.0
[conda] Could not collect

==============================
         vLLM Info
==============================
ROCM Version                 : Could not collect
vLLM Version                 : git sha: e37ff5b5c, date: 20260319
vLLM Build Flags:
  CUDA Archs: 9.0 10.0; ROCm: Disabled
GPU Topology:
        GPU0    GPU1    GPU2    GPU3    GPU4    GPU5    GPU6    GPU7    NIC0    NIC1    NIC2    NIC3    NIC4    NIC5    NIC6    NIC7    NIC8    CPU Affinity    NUMA Affinity   GPU NUMA ID
GPU0     X      NV18    NV18    NV18    NV18    NV18    NV18    NV18    PIX     NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     0-31,64-95      0               N/A
GPU1    NV18     X      NV18    NV18    NV18    NV18    NV18    NV18    NODE    PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     0-31,64-95      0               N/A
GPU2    NV18    NV18     X      NV18    NV18    NV18    NV18    NV18    NODE    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     0-31,64-95      0               N/A
GPU3    NV18    NV18    NV18     X      NV18    NV18    NV18    NV18    NODE    NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     0-31,64-95      0               N/A
GPU4    NV18    NV18    NV18    NV18     X      NV18    NV18    NV18    SYS     SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    32-63,96-127    1               N/A
GPU5    NV18    NV18    NV18    NV18    NV18     X      NV18    NV18    SYS     SYS     SYS     SYS     SYS     NODE    PIX     NODE    NODE    32-63,96-127    1               N/A
GPU6    NV18    NV18    NV18    NV18    NV18    NV18     X      NV18    SYS     SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    32-63,96-127    1               N/A
GPU7    NV18    NV18    NV18    NV18    NV18    NV18    NV18     X      SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    PIX     32-63,96-127    1               N/A
NIC0    PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS      X      NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS
NIC1    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     NODE     X      NODE    NODE    NODE    SYS     SYS     SYS     SYS
NIC2    NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     NODE    NODE     X      NODE    NODE    SYS     SYS     SYS     SYS
NIC3    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     NODE    NODE    NODE     X      NODE    SYS     SYS     SYS     SYS
NIC4    NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE     X      SYS     SYS     SYS     SYS
NIC5    SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS      X      NODE    NODE    NODE
NIC6    SYS     SYS     SYS     SYS     NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     SYS     NODE     X      NODE    NODE
NIC7    SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     NODE    NODE     X      NODE
NIC8    SYS     SYS     SYS     SYS     NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE     X 

Legend:

  X    = Self
  SYS  = Connection traversing PCIe as well as the SMP interconnect between NUMA nodes (e.g., QPI/UPI)
  NODE = Connection traversing PCIe as well as the interconnect between PCIe Host Bridges within a NUMA node
  PHB  = Connection traversing PCIe as well as a PCIe Host Bridge (typically the CPU)
  PXB  = Connection traversing multiple PCIe bridges (without traversing the PCIe Host Bridge)
  PIX  = Connection traversing at most a single PCIe bridge
  NV#  = Connection traversing a bonded set of # NVLinks

NIC Legend:

  NIC0: mlx5_0
  NIC1: mlx5_1
  NIC2: mlx5_2
  NIC3: mlx5_3
  NIC4: mlx5_4
  NIC5: mlx5_5
  NIC6: mlx5_6
  NIC7: mlx5_7
  NIC8: mlx5_8

==============================
     Environment Variables
==============================
NVIDIA_VISIBLE_DEVICES=all
CUBLAS_VERSION=12.9.0.13
NVIDIA_REQUIRE_CUDA=cuda>=9.0
TORCH_CUDA_ARCH_LIST=9.0 10.0
NCCL_VERSION=2.26.5
NVIDIA_DRIVER_CAPABILITIES=compute,compat32,graphics,utility,video
NCCL_DEBUG=WARN
CUDA_ARCH_LIST=7.5 8.0 8.6 9.0 10.0 12.0
NCCL_IB_HCA==mlx5_0,mlx5_1,mlx5_2,mlx5_4,mlx5_5,mlx5_6,mlx5_7,mlx5_8
NVIDIA_PRODUCT_NAME=CUDA
CUDA_VERSION=12.9.0.043
NVIDIA_BUILD_REF=e72c4186e68b121b41799ac18defd049ccd0d9d1
CUBLASMP_VERSION=0.4.0.789
CUDA_VISIBLE_DEVICES=0,1,2,3,4,5,6,7
CUDA_VISIBLE_DEVICES=0,1,2,3,4,5,6,7
CUDNN_FRONTEND_VERSION=1.11.0
NCCL_IB_TIMEOUT=20
CUDNN_VERSION=9.10.1.4
LD_LIBRARY_PATH=/usr/local/cuda/compat/lib:/usr/local/nvidia/lib:/usr/local/nvidia/lib64
NVIDIA_BUILD_ID=275113427
CUDA_DRIVER_VERSION=575.51.03
NVIDIA_REQUIRE_JETPACK_HOST_MOUNTS=
NCCL_IGNORE_CPU_AFFINITY=0
PYTORCH_NVML_BASED_CUDA_CHECK=1
TORCHINDUCTOR_COMPILE_THREADS=1

---

from vllm import LLM, SamplingParams

llm = LLM(
    model="Qwen/Qwen3.5-397B-A17B",
    tensor_parallel_size=8,
    data_parallel_size=8,
    enable_expert_parallel=True,
)

output = llm.generate(
    ["What is 2+3?"],
    SamplingParams(max_tokens=128, temperature=0.0),
)
print(output[0].outputs[0].text)

---

Rank 0: tokens[0..N/8)    × weight_shard_0 → partial for tokens 0..N/8
Rank 1: tokens[N/8..2N/8) × weight_shard_1 → partial for tokens N/8..2N/8
...

RAW_BUFFERClick to expand / collapse

Your current environment

<details> <summary>The output of <code>python collect_env.py</code></summary>

==============================
        System Info
==============================
OS                           : Ubuntu 24.04.2 LTS (x86_64)
GCC version                  : (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0
Clang version                : Could not collect
CMake version                : version 3.31.1
Libc version                 : glibc-2.39

==============================
       PyTorch Info
==============================
PyTorch version              : 2.10.0+cu129
Is debug build               : False
CUDA used to build PyTorch   : 12.9
ROCM used to build PyTorch   : N/A

==============================
      Python Environment
==============================
Python version               : 3.12.12 (main, Oct 28 2025, 12:10:49) [Clang 20.1.4 ] (64-bit runtime)
Python platform              : Linux-5.15.0-1063-nvidia-x86_64-with-glibc2.39

==============================
       CUDA / GPU Info
==============================
Is CUDA available            : True
CUDA runtime version         : 12.9.41
CUDA_MODULE_LOADING set to   : 
GPU models and configuration : 
GPU 0: NVIDIA H100 80GB HBM3
GPU 1: NVIDIA H100 80GB HBM3
GPU 2: NVIDIA H100 80GB HBM3
GPU 3: NVIDIA H100 80GB HBM3
GPU 4: NVIDIA H100 80GB HBM3
GPU 5: NVIDIA H100 80GB HBM3
GPU 6: NVIDIA H100 80GB HBM3
GPU 7: NVIDIA H100 80GB HBM3

Nvidia driver version        : 535.216.03
cuDNN version                : Probably one of the following:
/usr/lib/x86_64-linux-gnu/libcudnn.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_adv.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_cnn.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_engines_precompiled.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_engines_runtime_compiled.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_graph.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_heuristic.so.9.10.1
/usr/lib/x86_64-linux-gnu/libcudnn_ops.so.9.10.1
HIP runtime version          : N/A
MIOpen runtime version       : N/A
Is XNNPACK available         : True

==============================
          CPU Info
==============================
Architecture:                         x86_64
CPU op-mode(s):                       32-bit, 64-bit
Address sizes:                        46 bits physical, 57 bits virtual
Byte Order:                           Little Endian
CPU(s):                               128
On-line CPU(s) list:                  0-127
Vendor ID:                            GenuineIntel
Model name:                           Intel(R) Xeon(R) Platinum 8462Y+
CPU family:                           6
Model:                                143
Thread(s) per core:                   2
Core(s) per socket:                   32
Socket(s):                            2
Stepping:                             8
Frequency boost:                      enabled
CPU(s) scaling MHz:                   114%
CPU max MHz:                          2801.0000
CPU min MHz:                          800.0000
BogoMIPS:                             5600.00
Flags:                                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
Virtualization:                       VT-x
L1d cache:                            3 MiB (64 instances)
L1i cache:                            2 MiB (64 instances)
L2 cache:                             128 MiB (64 instances)
L3 cache:                             120 MiB (2 instances)
NUMA node(s):                         2
NUMA node0 CPU(s):                    0-31,64-95
NUMA node1 CPU(s):                    32-63,96-127
Vulnerability Gather data sampling:   Not affected
Vulnerability Itlb multihit:          Not affected
Vulnerability L1tf:                   Not affected
Vulnerability Mds:                    Not affected
Vulnerability Meltdown:               Not affected
Vulnerability Mmio stale data:        Not affected
Vulnerability Reg file data sampling: Not affected
Vulnerability Retbleed:               Not affected
Vulnerability Spec rstack overflow:   Not affected
Vulnerability Spec store bypass:      Mitigation; Speculative Store Bypass disabled via prctl and seccomp
Vulnerability Spectre v1:             Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:             Mitigation; Enhanced / Automatic IBRS; IBPB conditional; RSB filling; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S
Vulnerability Srbds:                  Not affected
Vulnerability Tsx async abort:        Not affected

==============================
Versions of relevant libraries
==============================
[pip3] flashinfer-python==0.6.4
[pip3] nccl4py==0.1.1
[pip3] numpy==2.2.6
[pip3] nvidia-cublas-cu12==12.9.1.4
[pip3] nvidia-cuda-cupti-cu12==12.9.79
[pip3] nvidia-cuda-nvrtc-cu12==12.9.86
[pip3] nvidia-cuda-runtime-cu12==12.9.79
[pip3] nvidia-cudnn-cu12==9.19.0.56
[pip3] nvidia-cudnn-frontend==1.18.0
[pip3] nvidia-cufft-cu12==11.4.1.4
[pip3] nvidia-cufile-cu12==1.14.1.1
[pip3] nvidia-curand-cu12==10.3.10.19
[pip3] nvidia-cusolver-cu12==11.7.5.82
[pip3] nvidia-cusparse-cu12==12.5.10.65
[pip3] nvidia-cusparselt-cu12==0.7.1
[pip3] nvidia-cutlass-dsl==4.4.1
[pip3] nvidia-cutlass-dsl-libs-base==4.4.1
[pip3] nvidia-ml-py==13.590.48
[pip3] nvidia-nccl-cu12==2.27.5
[pip3] nvidia-nvjitlink-cu12==12.9.86
[pip3] nvidia-nvshmem-cu12==3.4.5
[pip3] nvidia-nvtx-cu12==12.9.79
[pip3] nvidia-resiliency-ext==0.5.0
[pip3] pyzmq==27.1.0
[pip3] torch==2.10.0+cu129
[pip3] torch_c_dlpack_ext==0.1.5
[pip3] torchaudio==2.9.0
[pip3] torchdata==0.11.0
[pip3] torchvision==0.25.0+cu129
[pip3] transformers==5.3.0.dev0
[pip3] triton==3.6.0
[conda] Could not collect

==============================
         vLLM Info
==============================
ROCM Version                 : Could not collect
vLLM Version                 : git sha: e37ff5b5c, date: 20260319
vLLM Build Flags:
  CUDA Archs: 9.0 10.0; ROCm: Disabled
GPU Topology:
        GPU0    GPU1    GPU2    GPU3    GPU4    GPU5    GPU6    GPU7    NIC0    NIC1    NIC2    NIC3    NIC4    NIC5    NIC6    NIC7    NIC8    CPU Affinity    NUMA Affinity   GPU NUMA ID
GPU0     X      NV18    NV18    NV18    NV18    NV18    NV18    NV18    PIX     NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     0-31,64-95      0               N/A
GPU1    NV18     X      NV18    NV18    NV18    NV18    NV18    NV18    NODE    PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     0-31,64-95      0               N/A
GPU2    NV18    NV18     X      NV18    NV18    NV18    NV18    NV18    NODE    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     0-31,64-95      0               N/A
GPU3    NV18    NV18    NV18     X      NV18    NV18    NV18    NV18    NODE    NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     0-31,64-95      0               N/A
GPU4    NV18    NV18    NV18    NV18     X      NV18    NV18    NV18    SYS     SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    32-63,96-127    1               N/A
GPU5    NV18    NV18    NV18    NV18    NV18     X      NV18    NV18    SYS     SYS     SYS     SYS     SYS     NODE    PIX     NODE    NODE    32-63,96-127    1               N/A
GPU6    NV18    NV18    NV18    NV18    NV18    NV18     X      NV18    SYS     SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    32-63,96-127    1               N/A
GPU7    NV18    NV18    NV18    NV18    NV18    NV18    NV18     X      SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE    PIX     32-63,96-127    1               N/A
NIC0    PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS      X      NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS
NIC1    NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     NODE     X      NODE    NODE    NODE    SYS     SYS     SYS     SYS
NIC2    NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     NODE    NODE     X      NODE    NODE    SYS     SYS     SYS     SYS
NIC3    NODE    NODE    NODE    NODE    SYS     SYS     SYS     SYS     NODE    NODE    NODE     X      NODE    SYS     SYS     SYS     SYS
NIC4    NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     NODE    NODE    NODE    NODE     X      SYS     SYS     SYS     SYS
NIC5    SYS     SYS     SYS     SYS     PIX     NODE    NODE    NODE    SYS     SYS     SYS     SYS     SYS      X      NODE    NODE    NODE
NIC6    SYS     SYS     SYS     SYS     NODE    PIX     NODE    NODE    SYS     SYS     SYS     SYS     SYS     NODE     X      NODE    NODE
NIC7    SYS     SYS     SYS     SYS     NODE    NODE    PIX     NODE    SYS     SYS     SYS     SYS     SYS     NODE    NODE     X      NODE
NIC8    SYS     SYS     SYS     SYS     NODE    NODE    NODE    PIX     SYS     SYS     SYS     SYS     SYS     NODE    NODE    NODE     X 

Legend:

  X    = Self
  SYS  = Connection traversing PCIe as well as the SMP interconnect between NUMA nodes (e.g., QPI/UPI)
  NODE = Connection traversing PCIe as well as the interconnect between PCIe Host Bridges within a NUMA node
  PHB  = Connection traversing PCIe as well as a PCIe Host Bridge (typically the CPU)
  PXB  = Connection traversing multiple PCIe bridges (without traversing the PCIe Host Bridge)
  PIX  = Connection traversing at most a single PCIe bridge
  NV#  = Connection traversing a bonded set of # NVLinks

NIC Legend:

  NIC0: mlx5_0
  NIC1: mlx5_1
  NIC2: mlx5_2
  NIC3: mlx5_3
  NIC4: mlx5_4
  NIC5: mlx5_5
  NIC6: mlx5_6
  NIC7: mlx5_7
  NIC8: mlx5_8

==============================
     Environment Variables
==============================
NVIDIA_VISIBLE_DEVICES=all
CUBLAS_VERSION=12.9.0.13
NVIDIA_REQUIRE_CUDA=cuda>=9.0
TORCH_CUDA_ARCH_LIST=9.0 10.0
NCCL_VERSION=2.26.5
NVIDIA_DRIVER_CAPABILITIES=compute,compat32,graphics,utility,video
NCCL_DEBUG=WARN
CUDA_ARCH_LIST=7.5 8.0 8.6 9.0 10.0 12.0
NCCL_IB_HCA==mlx5_0,mlx5_1,mlx5_2,mlx5_4,mlx5_5,mlx5_6,mlx5_7,mlx5_8
NVIDIA_PRODUCT_NAME=CUDA
CUDA_VERSION=12.9.0.043
NVIDIA_BUILD_REF=e72c4186e68b121b41799ac18defd049ccd0d9d1
CUBLASMP_VERSION=0.4.0.789
CUDA_VISIBLE_DEVICES=0,1,2,3,4,5,6,7
CUDA_VISIBLE_DEVICES=0,1,2,3,4,5,6,7
CUDNN_FRONTEND_VERSION=1.11.0
NCCL_IB_TIMEOUT=20
CUDNN_VERSION=9.10.1.4
LD_LIBRARY_PATH=/usr/local/cuda/compat/lib:/usr/local/nvidia/lib:/usr/local/nvidia/lib64
NVIDIA_BUILD_ID=275113427
CUDA_DRIVER_VERSION=575.51.03
NVIDIA_REQUIRE_JETPACK_HOST_MOUNTS=
NCCL_IGNORE_CPU_AFFINITY=0
PYTORCH_NVML_BASED_CUDA_CHECK=1
TORCHINDUCTOR_COMPILE_THREADS=1

</details>

🐛 Describe the bug

When running Qwen3.5 MoE models (e.g., Qwen/Qwen3.5-397B-A17B) with Expert Parallelism enabled and TP > 1 and DP > 1, the model produces completely garbled output. The root cause is that the Shared Expert computation is incorrect under the use_sequence_parallel_moe code path.

Model: Qwen/Qwen3.5-397B-A17B (512 routed experts, 1 shared expert)

Configuration: 8 nodes × 8 GPUs, TP=8, DP=8 (EP=64)

from vllm import LLM, SamplingParams

llm = LLM(
    model="Qwen/Qwen3.5-397B-A17B",
    tensor_parallel_size=8,
    data_parallel_size=8,
    enable_expert_parallel=True,
)

output = llm.generate(
    ["What is 2+3?"],
    SamplingParams(max_tokens=128, temperature=0.0),
)
print(output[0].outputs[0].text)

Analysis

This is correct for routed experts — the EP all-to-all mechanism handles chunked tokens properly.

Rank 0: tokens[0..N/8)    × weight_shard_0 → partial for tokens 0..N/8
Rank 1: tokens[N/8..2N/8) × weight_shard_1 → partial for tokens N/8..2N/8
...

Before submitting a new issue...

Make sure you already searched for relevant issues, and asked the chatbot living at the bottom right corner of the documentation page, which can answer lots of frequently asked questions.

extent analysis

Fix Plan

To fix the issue with the shared expert computation in the use_sequence_parallel_moe code path, we need to ensure that all ranks process the same tokens when computing the shared expert output. Here are the steps to fix the issue:

Modify the Qwen3NextSparseMoeBlock.forward() method to handle the shared expert computation correctly when use_sequence_parallel_moe is True.
Use all_gather to gather the input tokens from all TP ranks, so that each rank has all the tokens.
Compute the shared expert output using the gathered tokens and the TP-sharded weights.
Use reduce_results=True in the ColumnParallelLinear and RowParallelLinear layers to combine the partial sums from different weight shards.

Here is an example code snippet:

def forward(self, input_ids, attention_mask, **kwargs):
    if self.use_sequence_parallel_moe:
        # Gather input tokens from all TP ranks
        gathered_input_ids = self.all_gather(input_ids)
        gathered_attention_mask = self.all_gather(attention_mask)

        # Compute shared expert output using gathered tokens and TP-sharded weights
        shared_expert_output = self.shared_expert_mlp(gathered_input_ids, gathered_attention_mask)

        # Combine partial sums from different weight shards
        shared_expert_output = self.reduce_results(shared_expert_output)

        return shared_expert_output

Note that this is a simplified example and may require additional modifications to work correctly with the rest of the codebase.

Verification

To verify that the fix worked, you can test the model with the same configuration and input as before, and check that the output is no longer garbled. You can also add additional tests to ensure that the shared expert computation is correct in different scenarios.

Extra Tips

Make sure to test the fix thoroughly to ensure that it works correctly in all scenarios.
Consider adding additional logging or debugging statements to help diagnose any issues that may arise.
If you encounter any issues while implementing the fix, consider seeking help from the community or the developers of the vllm library.

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vllm - ✅(Solved) Fix [Bug]: Shared Expert output is incorrect under Sequence Parallel MoE (EP + TP > 1 + DP > 1) for Qwen3.5 MoE models [2 pull requests, 1 comments, 2 participants]

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Error Message

Root Cause

Fix Action

Fix / Workaround

============================== CPU Info

PR fix notes

PR #5: add Qwen3.5-9B megatron nightly test

Description (problem / solution / changelog)

Summary

Changed files

PR #2151: feat: add Qwen3.5 & GLM-4.7-Flash model support

Description (problem / solution / changelog)

Summary

Offline Experiments

Known Issues

Changed files

Code Example

Your current environment

🐛 Describe the bug

Analysis

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Fix Plan

Verification

Extra Tips

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